Staff Engineer, CPU Core Verification

Tenstorrent$100K — $500K *
Information Technology
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • 8+ years in CPU verification or a related digital design field.
  • In-depth understanding of high-performance out-of-order CPU microarchitecture.
  • Proficient in RTL, waveforms, logs, and handling complex debugging scenarios.
  • Strong communication skills to collaborate with design, DV, emulation, and post-silicon teams.

Responsibilities

  • Plan and execute functional verification for CPU core features and microarchitectural scenarios.
  • Develop UVM, assembly, and C/C++ stimulus for comprehensive ISA and microarchitecture coverage.
  • Create and debug C++ functional models for RISC-V extensions and components like APIC and IOMMU.
  • Analyze simulation and emulation regressions using waveforms, logs, and RTL insights.
  • Build and enhance coverage models to monitor and achieve architectural and microarchitectural coverage.
  • Refine core, cluster, and chip-level testbenches along with debugging infrastructure.
  • Collaborate with design and test teams to ensure robust CPU core and cluster delivery.

Benefits

  • Competitive compensation package with a base and variable component.
  • Hybrid work model based in Austin, TX or Santa Clara, CA.
  • Opportunity to work with innovative high-performance RISC-V CPU technology.
Full Job Description
You will own CPU core-level verification, shaping how our out-of-order RISC-V CPUs behave in silicon.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are
  • You bring 8+ years in CPU verification or closely related digital design.
  • You know high-performance out-of-order CPU microarchitecture in depth.
  • You work comfortably with RTL, waveforms, logs, and complex debug scenarios.
  • You communicate clearly across design, DV, emulation, and post-silicon teams.


What We Need
  • Plan and drive functional verification for CPU core features and microarchitectural scenarios.
  • Develop UVM, assembly, and C/C++ stimulus for ISA and microarchitectural coverage.
  • Develop/debug C++ functional models of RISC-V extensions and un-core components such as APIC and IOMMU.
  • Debug simulation and emulation regressions using waveforms, logs, and RTL understanding.
  • Build and refine coverage models to track and close architectural and microarchitectural coverage.
  • Improve core, cluster, and chip-level testbenches and debug infrastructure.
  • Support design bring-up across simulation, emulation, and post-silicon environments.
  • Collaborate with design, test, and validation to deliver robust CPU cores and clusters.


What You Will Learn
  • How Tenstorrent designs and validates high-performance RISC-V CPU cores and clusters.
  • Techniques for spanning pre-silicon, emulation, and post-silicon verification with shared stimulus.
  • Ways to scale coverage, debug, and infrastructure across multiple CPU programs.
  • How open hardware and software fit into Tenstorrent's broader compute roadmap.


Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits

About Tenstorrent

Tenstorrent is a semiconductor company that designs and develops computer processors for artificial intelligence and machine learning applications. The company's processors are designed to be energy-efficient and scalable, and are used by a range of businesses, from small startups to large enterprises. Tenstorrent was founded in 2016 and is headquartered in Toronto, Ontario.
Learn more about Tenstorrent
Size
51 employees
Industry
Founded
2016

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