• Verification of DDR6 Data Buffer to meet functional and performance specifications. • Be able to integrate and test on System-level and block level using UVM methodology • Support in developing verification plan based on specifications. • Support in Verification planning, maintenance, feature extraction, verification tests, coverage and checker development. • Develop efficient, reusable state-of-the-art verification environments and testbench structures. • Optimize solutions for key indicators such as reusability, performance and ease of use • Identify and communicate improvements that may ease verification and/or improve design behavior. • Support in optimizing UVM based testbench. • Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User. • Participate in feasibility studies. Qualifications • Drive the Memory interface products verification effort, including defining the verification strategy, developing test plans, coverage, and executing tests. • Drive and quality control the creation of a verification test plan. • Work closely with the design team to ensure that the design meets the requirements and is testable. • Identify and drive improvements to the verification process to ensure the highest levels of quality and efficiency. • Drive and monitor coverage of design verification. • Provide regular updates to management on the status of the verification effort. Education • Masters in Electrical Engineering, Computer Engineering, or equivalent with 6+ years of experience. • Bachelor's Degree in Electrical Engineering, Computer Engineering, or equivalent with 8+ years of experience Videos To Watch https://www.youtube.com/embed/k-zs4tB6nNc