Job Description:

About the Role

SiFive is looking for a Staff Design Verification Engineer to drive verification of high-performance CPU core functionality, with primary focus on ALU and integer-execution microarchitecture.

This is a Staff individual-contributor role within the CPU Design Verification organization, focused on high-performance out-of-order CPU core development.

The role spans core execution areas such as ALU pipelines, issue/dispatch interactions, dependency and forwarding behavior, replay and recovery handling, exception behavior, and related midcore control interactions. We are looking for an engineer who can independently own complex verification problems, define verification strategy early, identify microarchitectural risk, and raise verification quality across the broader CPU DV effort.

You will work closely with architecture, RTL, performance, and verification teams to ensure design intent is captured correctly, difficult corner cases are verified thoroughly, and signoff quality is achieved with strong technical judgment and scalable methodology.

• Own verification planning and execution for ALU- and execution-focused CPU core functionality, from block-level verification through core-level integration and signoff.

• Drive verification strategy, test planning, debug, coverage analysis, and closure for complex execution-pipeline behaviors and microarchitectural interactions.

• Define effective verification approaches for challenging ALU-related behaviors such as arithmetic and logical execution correctness, compare and branch-condition generation, operand dependency handling, bypass and forwarding behavior, replay scenarios, flush and recovery interactions, exception behavior, and issue/dispatch to execute/commit pipeline interactions.

• Verify corner-case interactions between ALU execution and surrounding core logic, including scoreboarding, operand readiness, structural conflicts, speculative execution effects, and interaction with branch, load/store, and commit behavior.

• Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models that expose corner cases and improve bug-finding efficiency.

• Partner closely with architecture and design teams from early feature-definition stages to review specifications, identify ambiguity, and improve design debugability and verification completeness.

• Drive efficient failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.

• Contribute reusable methodology, automation, and infrastructure that improve productivity and verification quality across future CPU core programs.

• Mentor other engineers through technical reviews, debugging guidance, and stronger verification practices.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• 7+ years of relevant experience in ASIC, CPU/core, or SoC design verification, with strong hands-on ownership of complex verification problems appropriate for a Staff role.

• Strong hands-on experience with SystemVerilog-based verification and modern verification methodologies.

• Direct experience with CPU/core verification and strong understanding of computer architecture and CPU microarchitecture.

• Experience verifying one or more CPU execution areas such as ALU pipelines, midcore execution/control logic, issue and dispatch behavior, dependency handling, forwarding, replay, or related integer-execution functionality.

• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.

• Strong debugging skills and the ability to translate architectural intent into effective verification strategy and execution.

• Familiarity with Python, C/C++, or similar scripting/programming languages used for DV infrastructure and automation.

• Direct experience with high-performance out-of-order CPU core verification.

• Experience verifying ALU microarchitectural behaviors such as integer arithmetic and logical operations, compare/condition evaluation, flag or condition-code generation, dependency tracking, forwarding correctness, replay, flush, and recovery behavior.

• Experience verifying execution-pipeline correctness across issue, operand collection, execute, writeback, and commit boundaries.

• Experience developing high-value assertions, checkers, and scoreboards for control-heavy, dependency-sensitive, or timing-sensitive CPU behavior.

• Experience using formal verification, emulation, or acceleration for high-risk or hard-to-observe verification problems.

• Experience collaborating effectively with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.

• Experience influencing verification methodology beyond immediate ownership scope through reusable infrastructure, automation, or technical leadership.

You will be part of a high performance Out-of-Order Core team that focuses on verification of components such as Frontend, Mid-Core, Load-Store Unit, Integer and Floating Execution Unit, as well as Vector Unit that implement the latest RVV.

BS/MS Degree in EE, CE or CS

5-8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verification

Deep understand of computer architecture is desired

Experienced developer using Object Oriented Programing principles

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in