10+ years of experience in STA (Static Timing Analysis) engineering
Proficient in RTL (Register Transfer Level) design concepts
Experienced with synthesis tools and capable of debugging related warning and error messages
Knowledge in scan insertion techniques
Hands-on experience with functional equivalence tools and netlist modifications
Expertise in logical equivalence checking and debugging techniques
Strong skills in timing closure and constraints feedback to RTL designers
Responsibilities
Conduct static timing analysis to validate design performance
Debug synthesis warnings and errors effectively
Implement scan insertion for testability
Collaborate with RTL designers to interpret and implement design changes
Utilize formal verification tools for logical equivalence checking
Ensure timing closure for high-performance designs
Provide feedback on constraints to optimize RTL designs
Benefits
Long-term contract of 12+ months
Opportunity to work in a vibrant tech hub
Engagement with cutting-edge tools and technologies
Collaborative work environment with opportunities for knowledge sharing
Full Job Description
Job Profile: STA Engineer
Experience: 10+ Years
Duration: 12+ Months
Location: Sunnyvale, CA
Basic Knowledge on RTL
Synthesys ( able to understand and debug all the Warning and Error messages )
Scan insertion.
Handle on Functional eco ( with conformal tool and if the design change is minimum able to edit the netlist by looking at the RTL change with the help of RTL designer)
Logical equivalence ( Formality/Conformal ); Need deep knowledge on debug
Timing closure
Understanding on constraints and able to give feedback to the RTL designer.
Tool experience: Synopsys DC, Formality, Primetime and Cadence conformal.
