Sr. Staff Engineer, AMS Design

Ayar Labs

$180K — $223K *
Telecommunications & Hardware
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • M.S. in Electrical Engineering
  • 6+ years in analog/mixed signal design
  • Experience with high speed analog blocks like PLLs and multi-phase generation
  • Proficient in Cadence design environment and mixed-signal simulation
  • Design experience in FinFet CMOS (7nm or below) with 50Gb/s data rates or RF circuits at 25GHz.

Responsibilities

  • Architect and design high speed signal paths for optical links
  • Collaborate with optical and digital teams to create mixed-signal control loops
  • Design circuits such as oscillators and linear regulators
  • Define, run, and automate verification simulations
  • Create documentation for design review and testing
  • Perform post-silicon bring-up of circuits in the lab

Benefits

  • On-site work environment in San Jose
  • Opportunity to work in a dynamic startup setting
  • Collaboration with talented IC design team
  • Exposure to cutting-edge optical and digital technologies
  • Ability to influence design specifications and project outcomes
Full Job Description
Sr. Staff Engineer, AMS Design

Location: San Jose (on-site)

As an Analog and Mixed Signal Design Engineer, you will design various blocks such as oscillators, high speed transmitters/receivers, biasing circuits, linear regulators, ADCs/DACs, and others. You will work as a part of a small IC design team in a dynamic startup environment. The ideal candidate is a hands-on self-starter who is able to develop design specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.

Key Responsibilities:
  • Architect and design high speed signal path for high bandwidth optical links
  • Work closely with optical and digital design teams to architect mixed-signal control loops
  • Design analog/mixed signal circuits such as oscillators, high speed transmitters/receivers, amplifiers, biasing circuits, linear regulators, ADCs/DACs, and others
  • Define, run, and automate sign-off verification simulations
  • Create design review and testing documentation
  • Perform post-silicon bring-up of circuits in lab


Required Qualifications:
  • M.S. in Electrical Engineering
  • 6+ years of work experience in analog/mixed signal design
  • Experience designing high speed analog blocks such as PLLs, clock distribution and multi-phase generation, high swing transmit drivers, high speed receive analog front ends.
  • Proficient with Cadence design environment and mixed-signal simulation (ADE, Layout, Spectre)
  • Have experience designing in FinFet CMOS (7nm or below) at data rates of at least 50Gb/s and/or RF circuits operating at 25GHz or above


Preferred Qualifications:
  • Ph.D.
  • Demonstrated experience in deploying SerDes into a high-volume product
  • A good understanding of high-speed design/layout considerations, such as parasitics, crosstalk isolation, supply and bias distribution, etc.
  • Able to develop adaptation/calibration algorithms for precision design
  • Experience with silicon bring-up, debug, and evaluation
  • Programming experience in Python and SKILL.


Salary range: $180,000 - $223,000

NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.

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