About the roleWe are looking to add a Sr. Design Verification Engineer to our team in Dallas, TX.
What you'll do- Read and understand IP specification
- Write and edit C testcases to run on mature SOC DV RTL simulation environment based on existing test plan
- Run and debug simulations using Cadence simulation toolchain
- Report on progress, file bug tickets, summarize issues
- Verification planning, testbench development, test case development, test case debug, coverage analysis, and metric/status reporting.
- Testbench development will include defining the architecture and implementation of: directed random test generators, coverage models, reference models and bus functional models.
Qualifications- Strong C programming ability (bare metal, driver code, etc.)
- Strong HW debugging experience
- Embedded software/hardware debug
- 6-10+ years of experience
- Preferred experience with defense industries previously.
Talent101 pays referral fees.
