Advanced Micro Devices, Inc

SR ASIC Design Engineer - Networking/ DPU/ AI Systems

Advanced Micro Devices, Inc • $130K — $180K *
Santa Clara, CA 95051In-Person
Information Technology
5 - 7 years of experience
Reposted 1 month ago
Job Overview by Ladders

Qualifications

  • 5+ years of hands-on experience in ASIC/SoC development from architecture to silicon bring-up
  • Proven experience with embedded SoC architectures, including CPUs and NoCs using AMBA protocols
  • Strong expertise in PCIe and DMA architectures
  • Experience with SoC IP generation and configuration tools
  • Proficiency in RTL design using SystemVerilog / Verilog
  • Demonstrated success in delivering production-grade ASIC or SoC silicon
  • Ability to collaborate effectively with cross-functional teams

Responsibilities

  • Lead the design and integration of embedded subsystems for AI networking ASICs
  • Drive integration using SoC IP tools and configuration frameworks
  • Design and integrate PCIe subsystems and DMA engines
  • Own and review architectures for boot flows and security initialization at SoC level
  • Support chiplet-based SoC integration and system-level considerations
  • Participate in system-level validation and bring-up of chiplet-based SoCs
  • Drive the quality implementation of RTL across multiple IP blocks
  • Assist in all ASIC development lifecycle activities, from synthesis to post-silicon bring-up
  • Debug complex SoC integration issues in various environments
  • Explore and adopt AI-assisted design tools to enhance development efficiency

Benefits

  • Comprehensive health and wellness packages
  • Paid time off and flexible work arrangements
  • Retirement savings plans with company match
  • Ongoing training and career development opportunities
  • Employee discounts and perks
Full Job Description
THE TEAM:

Our group, NTSG, develops advanced system solutions that combine ASIC, hardware, and software to enable next-generationAI networking workloads. We are building highly integrated, high-performance networking systems and are looking for experienced ASIC engineers to help drive development from architecture through production.

THE ROLE:

We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL architectureanddesign through tapeout, silicon bring-up, and mass production.

THE PERSON:

We are seeking a Senior ASIC Design Engineer with seasonedexperience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL architectureanddesign through tapeout, silicon bring-up, and mass production.

KEY RESPONSIBILITIES:

  • Architect and design key blocks for next-generationDPU ASICstargeting AI networking workloads
  • Contribute across the full ASIC development lifecycle
    • architecture definition
    • microarchitecture and RTL design
    • design reviews
    • implementation support
    • tapeout
    • silicon bring-up
    • production ramp and mass deployment support
  • Collaborate on advanced network processing engines, including P4-based, protocol-independent packet processing solutions
  • Design and implement high-speed, complex ASIC blocks for networking and data movement applications
  • Work closely with verification, modeling, software, and hardware teams to ensure functional correctness and system-level performance
  • Debug and resolve issues across simulation, emulation, lab bring-up, and post-silicon phases
  • Contribute to performance, power, and area optimization
  • Support integration of ASIC IPs into larger SoC and system architectures
  • Produce high-quality design documentation and participate in technical reviews


REQUIRED QUALIFICATIONS:
  • Seasoned ASIC design experience
  • Proven hands-on experience developing high-speed, complex ASICs
  • Strong experience across the complete ASIC development cycle, fromRTL architecture to tapeout to massproduction
  • Solid background in networking and packet-processing architectures
  • Experience collaborating across:
    • Verification
    • Modeling
    • Software
    • Hardware/system teams
  • Strong RTL design skills in:

    • Verilog
    • SystemVerilog


  • Strong programming skills in:
    • C/C++
  • Scripting experience in:
    • Python
    • Tcl
    • Shell

PREFERRED QUALIFICATIONS:

  • Experience designing complex ARM- or RISC-V-based SoC ASICs
  • Hands-on experience building complex Network-on-Chip (NoC) architectures
  • Strong knowledge of AXI / AMBA protocols
  • Familiarity with P4, programmable packet-processing pipelines, or protocol-independent networking architectures
  • Experience with post-silicon debug, bring-up, and production support
  • Experience with high-performance interconnect, data movement, and SoC integration
  • Self-motivated engineer with strong ownership and execution skills
  • Strong problem-solving ability and willingness to take on new technical challenges
  • Continuous learner who thrives in a fast-moving environment
  • Excellent communication and cross-functional collaboration skills


ACADEMIC CREDENTIALS:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field

LOCATION:

Santa Clara, CA

#LI-BW1

#LI-hybrid

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Manufacturing & Automotive
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ
AMD
* Ladders Estimates

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