Qualifications

• Master’s degree in Electrical, Electronics, or Computer Engineering with 0-5 years’ experience.
• Strong foundation in computer architecture, logic design, and VLSI design.
• Proficiency in Verilog, System Verilog, and experience with Perl and other scripting languages.
• Practical skills in design verification, functional coverage, and code analysis.
• Capability to write assembly language and debug synthesis and timing issues.
• Excellent communication skills and a track record as a collaborative team player.

Responsibilities

• Design and implement video compression, image processing, vector processing, and neural network accelerator logics.
• Perform logic design, implementation, and verification using Verilog, System Verilog, and relevant programming languages.
• Synthesize and optimize RTL to meet timing, area, and power constraints.
• Develop and refine front-end methodologies and tool flows.
• Participate actively in chip bring-up, testing, and troubleshooting processes.
• Analyze code and functional coverage to guide and improve verification efforts.

Benefits

• Initial RSU grants for new hires with the potential for annual RSU grants.
• Highly competitive benefits package.