Job Duties:- Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties.
- Provide technical support to Cadence customers in the areas of Digital Design Implementation and Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff.
- Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules.
- Conduct technical presentations and product demonstrations.
- Drive technical evaluations and benchmarks to success.
- Work closely with R&D to enhance the tools and methodologies to meet and exceed customers' requirements.
- Drive adoption and proliferation of Cadence tools and technologies.
- Amend and augment the flow as needed using Tcl and other programming skills to meet objectives and improve results and flows.
- Capture best practices and lessons learned from current evaluations and benchmarks and utilize to improve efficiency and success rate in next engagements.
- Provide technical support when developing business case for process improvement projects.
- Provide mentorship to junior engineers.
- Some telecommuting permitted.
- Must be available to work on projects at various, unanticipated sites throughout the United States.
Qualifications: - Master's degree in Electrical Engineering, Electronic Engineering, or related field and
- Minimum three (3) years of experience in the job offered or in a related occupation.
- Utilize Innovus or Fusion Compiler to implement block implementation closing timing, power, and area goals
- Register-Transfer Level (RTL) to GDSII flow, including Verilog or Very High-Speed Integrated Circuit Hardware Description Language (VHDL) synthesis and place and route with signoff on lower technology nodes including N5 and below
- Timing Analysis utilizing competitive place and route tools including Innovus, Tempus, Fusion Compiler, and PrimeTime
- Understanding of place and route, including RTL synthesis, floorplan, placement, routing with timing, area, power and design rule checks (DRC) closure for technology nodes including 7nm and below
- Central processing unit (CPU) physical design closure utilizing place and route industry standard tools including Innovus and Fusion compiler
- CPU and graphics processing unit (GPU) architecture-based design and understanding for closing gigahertz frequency challenge
- Tackling challenges associated with power, timing, variability and reliability in digital circuits at nanometer nodes including 7nm and 5nm
- Very-large-scale integration (VLSI) Circuit design including power, performance, area (PPA) analysis and standard cell library development for deep sub-micron technologies including 7nm and below
- Must be available to work on projects at various, unanticipated sites throughout the United States.
The annual salary range for California is $171,704 to $191,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the base salary range is a guideline, and individual total compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
