Job Details:
Job Description:
The RET DR and Tech Def team uses current and future lithography manufacturing tools to drive Design and process Technology Co-optimization (DTCO) as well as Design For Yield (DFY) to enable advanced node definition and extend the limits of feature sizes that are patternable by Intel Foundry for semiconductor devices
Responsibilities/Duties:
• Must have strong problem-solving, and trouble shooting skills to apply to challenging technical problems
• Engage with semiconductor design teams, fab patterning teams and design customers to develop design rules that will enable a clear path to manufacturable products on a very strict timeline
• Maintain a deep understanding of VLSI physical design optimization to drive advanced node process innovation
• Research, development, and implementation of Resolution Enhancement Techniques (RET) for existing and novel process technologies
• Collaborate with process modules and integration teams to select operating points and develop Module Target Specs (MTS) that enable next generation layout patterns
• Maintain substantial knowledge of the state-of-the-art principles and theories in lithography, optics, photoresists, computer modeling, and software engineering
• Use predictive modeling, statistics, machine learning, automation capabilities and other data analysis techniques to collect, explore, and visualize fab process data that will enable rapid convergence to layouts that are manufacturable with high yield
Qualifications:
Minimum Qualifications:
• Degree in Engineering, Physical Science, Computer Science, or related fields.
• 3+ years of experience in the semiconductor industry with emphasis on physical design and layout optimization.
• 3+ years of experience working with process design rules or patterning modules to enable characterization and patterning viability assessment of next generation design layouts
Preferred Qualifications:
• External Customer Foundry Experience
• Experience as a Physical Design Engineer or a Backend Design Engineer
• Strong understanding of physical design layout for standard cell libraries, place and route, SRAM, or analog mixed signals
• Some experience with development of automation flows to enable DTCO acceleration
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $201,580.00-284,580.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
