Advanced Micro Devices, Inc

SoC Verification Engineer - NoC / UVM

Advanced Micro Devices, Inc • $120K — $150K *
San Jose, CA 95123In-Person
Telecommunications & Hardware
Less than 5 years of experience
Today
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Job Overview by Ladders

Qualifications

  • 5-7 years of experience in ASIC/SoC verification
  • Proficient in SystemVerilog and UVM methodologies
  • Strong understanding of digital design verification
  • Experience with NoC architectures is a plus
  • Familiar with formal verification using SVA
  • Analytical mindset with detail-oriented approach
  • Ability to collaborate effectively with global teams

Responsibilities

  • Lead verification of complex digital design blocks and understand specifications
  • Create comprehensive verification test plans with architects and engineers
  • Design testbenches in System Verilog and UVM for efficiency
  • Develop constrained-random and directed verification environments
  • Debug tests in collaboration with design engineers
  • Identify and write coverage measures for quality improvements
  • Perform coverage analysis to close verification holes

Benefits

  • Comprehensive health and wellness programs
  • Retirement savings plan with company match
  • Flexible work arrangements
  • Professional development and learning opportunities
  • Employee discounts and perks
Full Job Description
THE ROLE:

The verification team at AMD is looking for a Verification Engineer to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs.

THE PERSON:

You are a skilled verification engineer with strong expertise in SystemVerilog and UVM, and a solid understanding of ASIC/SoC verification methodologies. You have experience verifying complex digital designs, ideally including NoC architectures, and are proficient in constraint-random, coverage-driven, and formal verification (SVA). You are analytical, detail-oriented, and collaborative, with the ability to debug complex issues, drive verification closure, and effectively partner with global design and architecture teams while taking ownership of challenging problems.

KEY RESPONSIBILITIES:
  • Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
  • Interact with architects and design engineers to create a comprehensive verification testplan
  • Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
  • Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Identify and write coverage measures for stimulus quality improvements
  • Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

PREFERRED EXPERIENCE:
  • Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
  • Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
  • Strong understanding of different phases of ASIC and/or full custom chip development is required.
  • Experience in block level NOC (Net work on Chip) verification is a plus.
  • Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.
  • Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance FPGAs, SOCs and/or VLSI designs is a plus.
  • Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
  • Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus.


ACADEMIC CREDENTIALS:
  • Bachelors or Masters degree in computer engineering/Electrical Engineering


This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

Advanced Micro Devices, Inc. Careers

Join the innovative forefront of technology with a career at Advanced Micro Devices, Inc. (AMD), a leader in semiconductor development. As part of our global team, you will contribute to an organization renowned for its dedication to innovation, leadership, and diversity in the tech industry.

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Join a team of over 12,000 dedicated professionals at the intersection of technology, industry expertise, and digital innovation. At AMD, you will work on groundbreaking projects that shape the future of computing and graphics. Our collaborative environment encourages networking and the sharing of ideas across teams and disciplines.

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Manufacturing & Automotive
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ
AMD
* Ladders Estimates

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