Job Details:

Job Description:

About the Role

Altera is seeking an experienced SoC uArchitect / Architect to help define next-generation FPGA-based heterogeneous platforms for automotive, embedded AI, robotics, video/vision, and safety-critical edge applications. This role is intended for candidates with 8+ years of experience in SoC architecture, processor subsystem design, embedded systems, or heterogeneous compute platforms, with strong exposure to ARM-based SoC development and system-level architecture.

In this role, you will contribute to architecture and microarchitecture definition for ARM processor subsystems, safety islands, interconnect fabrics (AXI/APB), memory systems, and FPGA-to-processor integration for edge platforms. You will work across hardware, software, firmware, verification, and product teams to translate platform requirements into architecture specifications, microarchitecture definitions, IP requirements, and validation-ready designs.

This is a hands-on architecture role where you will be expected to engage deeply in microarchitecture definition, hardware/software interface design, performance tradeoffs, and system-level debug and analysis. Strong exposure to ARM-based SoCs, embedded platforms, or automotive systems is essential, along with a working understanding of how architecture decisions translate into RTL, firmware, and system behavior.

Experience with automotive concepts such as safety islands, fault containment, or ISO 26262 principles is highly valuable, as is experience in embedded AI, video/vision processing, or FPGA-based acceleration platforms.

Responsibilities

Responsibilities may include but are not limited to:

• Define system-level architecture and microarchitecture for FPGA-based heterogeneous SoC platforms targeting automotive, embedded AI, robotics, and edge applications
• Contribute to ARM processor subsystem architecture, including CPU integration, memory maps, interrupts, boot flows, clocks/resets, and software-visible interfaces
• Define and refine safety island and real-time subsystem architectures, including fault containment, diagnostics, watchdog mechanisms, and system monitoring
• Develop interconnect architecture across AXI/APB-based fabrics, including DMA flows, QoS considerations, and peripheral integration
• Define memory subsystem architecture including DDR interfaces, SRAM, caches, buffering strategies, and data movement optimization
• Support architecture definition for video/vision and sensor processing pipelines for real-time embedded applications
• Work on integration between ARM subsystems, FPGA fabric, accelerators, and firmware/software stacks
• Create architecture and microarchitecture specifications, register definitions, address maps, and performance requirements
• Collaborate with RTL, design verification, firmware, software, validation, and product teams to ensure architecture execution
• Participate in architecture reviews, performance analysis, emulation planning, and system debug activities
• Analyze system performance, identify bottlenecks, and support tradeoff analysis for power, performance, and area optimization
• Support pre-silicon and post-silicon debug efforts including firmware bring-up and system issue triage
• Translate platform and customer requirements into scalable architecture decisions and subsystem requirements

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$133,200 - $190,000USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations

Qualifications:

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
• 8+ years total experience in SoC architecture, embedded systems, processor subsystem design, or FPGA/ASIC development
• 3+ years experience in SoC or subsystem architecture definition (CPU, memory, interconnect, or platform-level architecture)
• 3+ years experience working with or designing ARM-based systems or embedded processor subsystems
• 3+ years experience in system-level hardware/software architecture (boot flows, memory maps, interrupts, registers, firmware interaction)
• 2+ years experience in interconnects and bus protocols such as AXI, AHB, APB, or equivalent SoC fabrics
• 2+ years experience in memory subsystem concepts including DDR, caching, or system memory hierarchy
• 2+ years experience working cross-functionally with RTL, firmware, verification, or validation teams
• 1+ year experience in performance analysis, bottleneck identification, or system-level debug
• Experience working on embedded systems, heterogeneous compute platforms, or SoC-based products
• Strong understanding of how architectural decisions translate into implementation across hardware and software stacks
• Experience participating in system-level debug, emulation, pre-silicon validation, or post-silicon bring-up activities

Preferred Qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field
• Experience with automotive SoC concepts including safety islands, fault isolation, watchdogs, or ISO 26262 fundamentals
• Exposure to embedded AI, edge computing, robotics, or video/vision processing systems
• Experience with Linux, RTOS, firmware, or low-level software on ARM-based systems
• Familiarity with PCIe, Ethernet, MIPI, USB, or similar high-speed interfaces
• Experience with FPGA-based acceleration or heterogeneous compute architectures
• Exposure to system-level performance modeling or architecture simulation tools
• Experience collaborating across architecture, RTL, firmware, and validation teams in complex SoC programs

Job Type:
Regular

Shift:
Shift 1 (United States of America)

Primary Location:
San Jose, California, United States

Additional Locations: