Minimum qualifications:- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 10 years of experience in power management or low power design/methodology.
- Experience with low power architecture and power optimization techniques (multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS, AVS)).
- Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization).
Preferred qualifications:- Master's degree or PhD in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance and power analysis.
- Experience with system-level power modeling, optimizations and analysis for one or more major SoC subsystems such as memory path, multimedia, etc.
- Excellent written and verbal communication skills, with the ability to work with cross-functional teams to drive consensus and influence product decisions.
- Exceptional leadership, organizational, communication, and persuasion skills.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) 20% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities- Lead the definition of power requirements for Tensor mobile SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints.
- Own and drive cross-functional teams to deliver on competitive power key performance indicator (KPIs) for one or more major SoC IPs such as memory subsystem, multimedia subsystem, etc.
- Propose and drive power optimizations throughout the design process from concept to mass productization.
- Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.
- Represent the status of SoC power to executive leadership team.
