Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience in DFT architecture, implementation, and verification for SoCs.
- Experience in silicon bring-up, debug, or validation of DFT features.
- Experience with industry-standard test methodologies and platforms, such as (but not limited to) ATE, MBIST, JTAG, or System Level Test (SLT).
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 10 years of experience in DFT architecture, implementation, and verification for SoCs.
- Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).
- Experience in DFT flow, including architecture, IP integration (e.g., Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
- Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).
- Knowledge of test standards (e.g., IEEE 1149.1, 1687) and test data formats (e.g., BSDL, STIL).
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a DFT Engineer you will be responsible for defining, implementing and deploying advanced Design-for-Test (DFT) methodologies including scan, MBIST, JTAG and iJTAG, for highly digital or mixed-signal chips or IPs. You will define silicon test strategies, DFT/DFD architecture, and create DFT and debug specifications for next generation SoCs. In partnership with the Silicon Engineering team, you will also be responsible for diagnosing memory and logic failures, increasing production quality, and enhancing yield and reducing test cost.
The US base salary range for this full-time position is $163,000-$237,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities- Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, memory built-in self-test (MBIST), automatic test pattern generation (ATPG) and instrument/joint test action group (I/JTAG), and associated boot up and execution sequences.
- Complete all test design rule checks (TDRC) and design changes to fix TDRC violations to achieve high test quality.
- Develop diagnostic databases, software and hardware for logic and memory fail debug.
- Design and implement system level test strategy.
- Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.
