Job Details:Job Description: As a Silicon Packaging Design Engineer, you will play a pivotal role in driving the development of advanced substrate designs, contributing to the creation of cutting-edge technology that fuels Intel's innovation. You will be responsible for the end-to-end development of substrate designs, from concept through tape-out, ensuring optimal performance, cost efficiency, and manufacturability. This position provides an exciting opportunity to work collaboratively with silicon and hardware teams, directly impacting Intel's success in delivering world-class solutions for high-performance applications.
Key Responsibilities
- Drive the physical layout and routing of package designs, ensuring alignment with silicon, package, and board performance requirements.
- Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs.
- Define and implement substrate design rules, conducting internal and external reviews to ensure designs meet quality standards.
- Analyze data, resolve Design Rule Checks (DRCs), and optimize package designs for manufacturability and performance.
- Collaborate with cross-functional teams to optimize pinout and silicon-package-board interactions.
- Complete documentation and collateral into the product lifecycle management system of record
Behavioral traits
- Problem-solving skills and a proactive approach to challenges.
- Excellent communication and interpersonal skills for effective cross-functional collaboration.
- Manage multiple tasks and projects simultaneously under tight deadlines.
Qualifications:Minimum qualifications are required to be initially considered for this position.
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This position is not eligible for Intel immigration sponsorship
Knowledge and/or experience listed below would be obtained through a combination of your school/work and/or classes and/or research and/or relevant previous job and/or internship experiences.
Minimum Qualifications
- Bachelors with 1+ years of experience or master’s degree with 6 months of experience in Electrical Engineering, Mechanical Engineering, or Material Sciences disciplines.
- 6+ months of experience with the following technical skills:
- Experience and/or familiarity with microelectronic package or PCB physical layout design and manufacturing process.
- Familiarity with package design tools like Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.
- Familiarity with physical layout aspects of substrate design, including custom layouts, floor plans, or schematic layout conversion.
Preferred Qualifications:
- Experience in microelectronic package substrate design, package I/O routing, and/or technology development.
- Familiarity with microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS.
- Experience with package design tools such as Package Layout Automation (PLA) and FIELD.
- Experience with scripting using Python, VB, C, or similar languages
Job Type:College Grad
Shift:Shift 1 (United States of America)
Primary Location: US, Arizona, Phoenix
Additional Locations:
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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