Advanced Micro Devices, Inc

Silicon Design Engineer

Advanced Micro Devices, Inc$130K — $155K *
Consumer Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • 5-7 years of experience in RTL-to-GDS physical implementation flow.
  • Expertise in digital ASIC/SoC design and verification processes.
  • Strong knowledge of CMOS fundamentals and semiconductor device physics.
  • Experience with advanced process technologies (7nm, 5nm, 3nm).
  • Proficiency in physical signoff methodologies and tools like STA, DRC/LVS.

Responsibilities

  • Drive timing-aware synthesis to generate optimized netlists.
  • Lead the physical design cycle from RTL to GDSII tapeout.
  • Perform Static Timing Analysis (STA) to validate design margins.
  • Execute physical signoff analyses alongside cross-functional teams.
  • Assist with post-silicon validation and debugging activities.

Benefits

  • Comprehensive health care coverage.
  • Retirement savings plans with employer contributions.
  • Paid time off and holidays.
  • Opportunities for professional development and advancement.
Full Job Description
THE ROLE:

We are seeking a highly motivated Silicon Design Engineer with strong RTL-to-GDS background and full ASIC design flow experience to join AMD's AECG Silicon Integration & Test team.

This role focuses on design and verification of advanced silicon testchips, including place-and-route, timing closure, physical verification, design signoff, and tapeout readiness. The successful candidate will work closely with front-end design, CAD, and silicon validation teams to deliver leading-edge FPGA and ASIC testchip solutions.

THE PERSON:

The ideal candidate is a hands-on backend design engineer with proven experience owning major portions of the RTL-to-GDS physical implementation flow. You should be comfortable working independently, driving implementation challenges to closure, collaborating across design teams, and delivering successful tapeouts. Experience in small, fast-moving environments where engineers take broad ownership is highly valued.

KEY RESPONSIBILITIES:
  • Drive the timing-aware/physical-aware synthesis flow using industry-standard tools (e.g., Design Compiler) to generate optimized netlists.
  • Lead the end-to-end digital ASIC/SoC physical design cycle from RTL handoff through GDSII tapeout, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, signal integrity optimization, physical verification, and design signoff.
  • Close SoC timing with Static Timing Analysis (STA) using tools such as PrimeTime to validate setup/hold margins across process, voltage, and temperature (PVT) corners.
  • Drive tapeout readiness by performing physical signoff analyses including IR drop, electromigration (EM), noise, DRC/LVS verification, and cross-functional reviews with RTL, DFT, package, and foundry teams.
  • Assist with post-silicon bring-up, debugging, and lab-based validation activities.


PREFERRED EXPERIENCE:
  • Expertise in digital ASIC/SoC implementation flows, including synthesis, floorplanning, power planning, placement, CTS, routing, timing closure, and physical signoff using industry-standard tools (Cadence Genus/Innovus and/or Synopsys Fusion Compiler).
  • Strong understanding of CMOS circuit design fundamentals, semiconductor device physics, signal integrity, power integrity, and device reliability mechanisms.
  • Proven experience delivering silicon across advanced process technologies, including FinFET (7nm/5nm/3nm) and emerging Gate-All-Around (GAA) nodes.
  • Hands-on experience with physical signoff methodologies, including STA, IR drop, electromigration (EM), DRC/LVS, noise analysis, and tapeout qualification.
  • Strong analytical and problem-solving skills, with experience debugging complex design implementation issues and driving cross-functional closure.
  • Experience with silicon bring-up, post-silicon validation, and laboratory test equipment is a plus.
  • Proficiency in Python, Tcl, and shell scripting for automation, flow development, and productivity enhancement.


ACADEMIC CREDENTIALS:

Preferably holds an advanced degree (PhD or MS) in electrical & electronics engineering or physical sciences; alternatively, a bachelor's degree and relevant industry experience is acceptable.

This role is not eligible for visa sponsorship.

#LI-DR2

Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ

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