Job Title: Senior Test Engineer for SOC Microprocessors

Location: Austin, (Oakhill, Office)

Role Summary:

• You will design, develop, and implement cost-effective methods of testing for IP on advanced nodes, working with the Design and Verification teams before tapeout.

• You will support qualification, characterization, and production test with diagnostic programs.   

Job Responsibility:

New Technology/Product Introduction (NTI/NPI) on microprocessors is not a simple task. We will challenge you to bring a flawless new product to market. Customers don’t want a product to be late, defective, or low performance.  To get high performance parts we must push the limits of the technology and the more you push, the more important the role of the Test Engineer.

This role is responsible for

• New Product Introduction via Characterization, Qualification, and Debug of new products.

• You will design, develop, and implement cost-effective methods of testing for IP on advanced nodes, working with the Design and Verification teams before tapeout.

• You will support qualification, characterization, and production testing by providing diagnostic programs. 

• You must understand the design of ATE hardware, especially at high speed

• You should have a good understanding of the semiconductor development process, including Verilog testbenches

• You should understand what goes wrong in semiconductor design and in semiconductor manufacturing and anticipate the required test strategy

• You understand the economics of semiconductor test

• You will work in an environment of continuous learning, and continuous improvement. We work as a team of engineers in a collaborative environment. We expect all our engineers to work together and learn from each other. We expect you to research the latest techniques as a life-long learner.

​Job Qualification:

• Bachelor's degree or above in Electrical Engineering

• 5+ years of recent experience in semiconductor test development, and/or some experience in silicon verification or emulation

• Have 5 years of hands-on experience with Advantest, Teradyne ATE, or System Level Test development on advanced FinFET or GAA SOCs, below 28nm

• Experience with AI processors, SERDES interfaces (PCIe, USB, MIPI, etc.), HVST, scan, MBIST, or analog test is a plus.

• Have flexible and diverse programming skills, including Verilog and Python

• Can exhibit a record of teamwork

• Good listener and good communicators

• Have a history of creative problem solving in semiconductor manufacturing test development and debug

• Good grasp of statistics and six sigma manufacturing

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