Job Description:

Microchip Technology FPGA Business Unit is seeking a highly skilled and experienced System Power Architect to join our dynamic team. The successful candidate will be responsible for leading cross-functional teams to deliver high-performance IP integrations into our FPGA products, that meet market & customer requirements across a broad range of use cases & application spaces.

This position is in the Silicon Architecture team of Microchip's FPGA Business Unit. Microchip is a major supplier of low-power, highly-reliable and highly-secure field-programmable gate arrays (FPGAs). Our FPGAs are used in a wide variety of use cases & applications, including embedded vision; digital signal processing; machine learning; industrial and medical equipment; satellites; and diverse defense applications. Microchip is also a pioneer in embedding RISC-V processors in FPGAs.

The successful applicant will work as part of a core team to develop future FPGA device products and will collaborate with other engineering disciplines to model, develop, verify, and integrate power efficiency solutions to meet aggressive power, performance and area (PPA) goals.

Key Responsibilities:

• Understand customer use cases and the role of power management architecture in overall system architecture.
• Lead cross-functional teams to analyze customer use cases & architect solutions to deliver high-performance, low power FPGA products that extend Microchip's power efficiency leadership.
• Develop pre-silicon power models and work with other architects to explore PPA trade-offs.
• Develop PDN models and architecture at system, package and chip levels.
• Collaborate with back-end implementation teams to define UPF/CPF (Unified Power Format / Common Power Format) specifications.
• Create product power architecture specifications that meet the power efficiency goals.
• Partner with CAD/EDA teams to integrate power analysis tools into the design flow.
• Work with firmware/software teams to define power management firmware, drivers, and runtime policies.
• Work with test, validation and characterization teams to define their respective plans.
• Work cross-functionally with other architects, designers, and back-end implementation teams.

Requirements/Qualifications:

• Strong understanding of CMOS power consumption (dynamic, static/leakage, short-circuit) and advanced process node challenges (FinFET, GAA).
• Knowledge of state-of-the-art FPGA power features.
• Expertise in low-power design techniques: power gating, clock gating, retention, multi-voltage design, DVFS.
• Hands-on experience with UPF/CPF and EDA power analysis tools.
• Ability to analyze workloads and build power models at different abstraction levels (system, microarchitecture, RTL).
• Experience in technical leadership and people management will be an advantage.
• Proven ability to work cross-functionally with other architects, designers, and back-end implementation teams (in hardware, firmware, software).
• BS degree or higher in EE, CS, CE or other applicable disciplines.
• 10+ years of industrial experience.

Travel Time:

0% - 25%

Physical Attributes:

Feeling, Hearing, Other, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements:

80% Sitting, 10% Walking, 10% Standing, Usual Business Hours

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:
Benefits of working at Microchip

The annual base salary range for this position, which could be performed in the US, is $90,000 - $232,000.*

*Range is dependent on numerous factors including job location, skills and experience.