Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
Minimum Qualifications:• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
Experience: Minimum 0 to 6 years of hands on experience in Synthesis and LECJob Role- Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.
- Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.
- Experience in all aspects of timing closure for multi-clock domain designs.
- Should be familiar with MCMM synthesis and optimization.
- Should have good understanding of low-power design implementation using UPF.
- Experience with scripting language such as Perl/ Python, TCL.
- Experience with different power optimization flows or technique such as clock gating.
- Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation
- Should be able to handle ECOs and formal verification and maintain high quality matrix
Skill Set- Proficiency in Python/Tcl
- Familiar with Synthesis tools (Fusion Compiler/Genus),
- Fair knowledge in LEC, LP signoff tools
- Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking
- Familiarity with standard software engineering practices like Version
- Control, Configuration Management, Regression is a plus
Pay range and Other Compensation & Benefits: $115,600.00 - $173,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
