Senior Signal Integrity Engineer

Amphenol

• $110K — $130K *
Technical Services
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • BS, MS, or PhD in Electrical Engineering or related field.
  • 5+ years of experience in high-speed signal integrity engineering.
  • Strong understanding of high-speed serial interfaces and networking systems.
  • Experience with 56G, 112G, and preferably 224G PAM4 technologies.
  • Experience developing products using DSPs and retimers.
  • Experience with active copper cables AEC, DACs, ACCs.
  • Strong understanding of PCB design, stack-ups, via optimization, and transmission line theory.

Responsibilities

  • Develop channel architectures for high-speed copper and optical interconnect products.
  • Perform pre-layout and post-layout SI simulations for channels operating at 224G PAM4 and beyond.
  • Analyze insertion loss, return loss, crosstalk, impedance discontinuities, and channel compliance.
  • Optimize PCB stack-ups, via structures, connector interfaces, cable constructions, and package transitions.
  • Collaborate with cable suppliers on manufacturing feasibility and performance optimization.
  • Evaluate and optimize high-speed channels utilizing DSPs and retimers.
  • Support device bring-up, characterization, and compliance testing.

Benefits

  • Collaborative work environment across multiple engineering disciplines.
  • Opportunities for hands-on laboratory validation and testing.
  • Engagement in cutting-edge technology involving next-generation high-speed networking.
  • Chance to work on industry-leading products like Active Electrical Cables and optical transceivers.
  • Involvement in cross-functional projects impacting design and manufacturing decisions.
Full Job Description
Position: Senior Signal Integrity Engineer High-Speed Active Electrical Cables

Location: Nashua, NH



Position Summary

We are seeking an experienced Signal Integrity (SI) Engineer to join our High-Speed I/O R&D team. The successful candidate will be responsible for the electrical design, simulation, validation, and optimization of next-generation Active Electrical Cables (AEC), optical transceivers, Linear Pluggable Optics (LPO), and high-speed networking products supporting 800G, 1.6T and future generation applications.

This role requires deep expertise in high-speed serial channels, DSPs, retimers, SerDes architectures, PCB design, cable assemblies, optical modules, and signal integrity analysis from concept through production.

Responsibilities

Signal Integrity Design & Analysis
  • Develop channel architectures for high-speed copper and optical interconnect products.
  • Perform pre-layout and post-layout SI simulations for channels operating at 224G PAM4 and beyond.
  • Analyze insertion loss, return loss, crosstalk, impedance discontinuities, and channel compliance.
  • Optimize PCB stack-ups, via structures, connector interfaces, cable constructions, and package transitions.
  • Develop channel budgets and link performance models.

AEC and Copper Interconnect Development
  • Design and evaluate Active Electrical Cable (AEC) architecture utilizing DSPs and retimers.
  • Perform channel simulations for DAC, ACC, and AEC products.
  • Collaborate with cable suppliers on manufacturing feasibility and performance optimization.

DSP & Retimer Integration
  • Evaluate and optimize high-speed channels utilizing DSPs and retimers from leading semiconductor vendors.
  • Analyze equalization performance, FEC impacts, CTLE, DFE, and adaptive link behavior.
  • Support device bring-up, characterization, and compliance testing.

Laboratory Validation
  • Develop correlation between simulation and measured performance.
  • Perform channel characterization using VNAs, TDRs, oscilloscopes, and BERT systems.
  • Analyze eye diagrams, COM, SNDR, BER, jitter, and equalization performance.
  • Support compliance testing and customer qualification activities.

Cross-Functional Leadership
  • Work closely with PCB design, mechanical, thermal, process, firmware, manufacturing, and supplier teams.
  • Drive technical decisions related to channel architecture, stack-up selection, and manufacturing tradeoffs.
  • Support customer design reviews and technical engagements.

Required Qualifications
  • BS, MS, or PhD in Electrical Engineering or related field.
  • 5+ years of experience in high-speed signal integrity engineering.
  • Strong understanding of high-speed serial interfaces and networking systems.
  • Experience with 56G, 112G, and preferably 224G PAM4 technologies.
  • Experience developing products using DSPs and retimers.
  • Experience with active copper cables AEC, DACs, ACCs.
  • Strong understanding of PCB design, stack-ups, via optimization, and transmission line theory.
  • Experience with S-parameter analysis and channel modeling.

Preferred Experience
  • Experience with QSFP-DD, OSFP, OSFP-XD I/O cable assembly products
  • Familiarity with Broadcom, Credo, Marvell, Astera Labs, or similar DSP/retimer solutions.
  • Familiarity with CMIS and MSA specifications.
  • Experience supporting NPI, qualification, and volume manufacturing.

Ansys HFSS, COM and IEEE channel compliance methodologies.

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