- Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.
- Drive SoC planning, integration strategy, execution schedules, risk management, and tape-out readiness.
- Lead cross-functional teams across digital design, verification, physical design, DFT, firmware, validation, packaging, and product engineering.
- Define chip-level architecture, integration requirements, performance targets, and power/area objectives.
- Drive technical decision-making and trade-off analysis across architecture, implementation, and product requirements.
- Oversee subsystem and IP integration, ensuring successful deployment of complex multi-domain SoCs.
- Partner with analog and SerDes teams to integrate high-speed interfaces and mixed-signal subsystems into the overall chip architecture.
- Lead design reviews, execution reviews, silicon readiness assessments, and post-silicon debug activities.
- Drive issue resolution across the development lifecycle and ensure successful first-pass silicon execution.
- Mentor senior engineers and provide technical leadership across multiple engineering organizations.
Qualifications- Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline.
- 20+ years of semiconductor industry experience with substantial leadership responsibility.
- Proven experience as a Chip Lead, SoC Lead, Technical Program Lead, or equivalent role for large-scale ASIC/SoC products.
- Demonstrated success leading advanced-node SoCs, preferably at 3nm and/or 5nm technology nodes.
- Deep understanding of SoC architecture, integration methodologies, and full-chip development flows.
- Strong experience working across:
- RTL Design, Design Verification, Physical Design, DFT, Static Timing Analysis, Low-Power Design Methodologies and Silicon Bring-up and Productization.
- Experience managing complex schedules, technical dependencies, and cross-functional execution across global teams.
- Strong communication, stakeholder management, and engineering leadership skills.
Preferred Qualifications: - Prior experience with:
- High-performance switching silicon
- Network-on-Chip (NoC) architectures
- Data movement and interconnect fabrics
- High-bandwidth memory-centric systems
- Complex multi-die or chiplet-based architectures
- Hands-on experience integrating:
- High-speed SerDes interfaces, Analog front-end (AFE) subsystems, Mixed-signal IPs and Advanced PHY technologies.
- Experience with high-bandwidth and low-latency interconnect technologies.
- Knowledge of packaging technologies and signal integrity considerations for high-speed systems.
- Experience in AI, HPC, networking, connectivity, data-center, or memory infrastructure products.
- Prior exposure to UALink, Ethernet switching, switch fabrics, or similar high-performance interconnect technologies is highly desirable.
Additional InformationThe expected annual pay range for this position is $230,000-300,000K. This position is also eligible for bonus opportunities. Please note that final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
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shape the future with us?
