Marvell Technology isseekinga highly experiencedaChipLeada to own theenda-atoa-aenddevelopment of a heterogeneous photonic chipletcomprisinga aahigha-aspeedelectrical IC with advanced analog SERDESa and aphotonic integrated circuit (PIC), brought together usingadvancedcoa-apackagedtechnologies.

This role requires technical breadth acrossmixeda-asignalSoC design, photonic integration,achipleta-astylepartitioning,afirmwareandapackagea-alevelcoa-adesign, along with proven leadership delivering complex silicon from concept throughsiliconbringa-aup, ATE, and system validation.

The ideal candidate has shippedhigha-aspeedI/O and/or optical products, understandselectricala-aopticaltradeoffs, and can act as the single technical owner across die, package, optics, and system boundaries.

Key Responsibilitiesa

• Own theaenda-atoa-aend producta designa spanninga Electrical IC, Photonic IC,a firmware stack,a anda advanced packaginga design.a

• Leadmicroa-aarchitectureand RTL developmenta forthe Electrical ICthata canincludehigh speed SERDESa and digital subsystems witha internally developeda IPsa anda industry standarda external IPs such asa UALink, UCIe,a etc.

• Collaboratewithverification team toensure robust functional and performance verificationspanningdigital RTL,a AMSand electrical-optical interfaces.

• Work closelywitha physical designand packaging teams onfloorplanning, physical implementation, timing,a power, anda physical verification closure.

• Partnerwith DFT experts toadriveDFT strategya for digital, analog SERDES, and systema-level testability.

• Partnerwitha photonicsteamto defineaPIC architecture, interfaces, and control schemes,anda ensure robustelectrical-opticalcoa-adesign.

• Collaboratewith test engineering to driveaATE enablement, test program development, and debug.

• Leadcross-functional team toa completeasystema-alevel validation, including boards, optics, firmware, and software interaction.Drivea roota-cause analysis across silicon, package, optics, and system domains.Mentorand developsenior engineers and influencea cross functional teamsacross disciplinesin a matrixed environment.

• Identifyandcommunicate technical status, risks, and tradeoffs to engineering and product leadership.

• Bachelor’s degree ina Computer Science,a Electrical Engineering,a ora related fields and 15+a years of relateda professional experiencea ORa Master’s degreea / aPhDa ina Computer Science,a Electricala Engineeringa ora related fields witha 8-12a years of experience.a

• 15+ years of experience inaASIC / SoC developmenta withaenda-atoa-aenda chip ownership.a

• Strong experience acrossa Microa-aarchitecturea and RTL design,a higha-a speedaanalog SERDES,a physical design anda signa-aoff,a DFT and manufacturing test,a advanced packaging anda chipleta-astylea integration,a posta-a silicona bringa-aup, ATE, and system validation.a

• Ability toclearly articulate architectural andimplementationtradeoffsa across performance, power, area, yield, cost, schedule, and risk.

• Strongtrack recordofdriving alignmentacrosscrossa-afunctionalteams with differing viewpoints in a matrixed environmentand drive solutions to toughengineering problems across the product stack.

• Excellent written and verbal communication skills, including leading technical reviews and communicating status, risks, and decisions to engineering and product leadershipat the executive level.

• While deepexpertiseacross all domains is not expected, the ideal candidate willdemonstratethea maturity andtechnical judgment tofoster a culture of cross-domain collaborationanda deal with conflicts in a calm and constructivefashion.



Preferred Qualifications

• Prior experience indelivery ofahigha-aspeedI/O and/or optical productsa into production.

• PriorexperienceasaChipLead, SoC Architect, oraSystema-aLevelTechnical Lead.