The SCG Architecture team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, and platform - translating product noise targets into shipped specifications, and feeding silicon findings back into the next generation's build. Success in this role requires strong systems thinking and a willingness to accept ambiguity. It also requires the ability to apply AI as a force multiplier while maintaining rigorous engineering judgment.
What you'll be doing:- Architect voltage-noise mitigation across the full stack - silicon, package, board, platform - and own the codesign trade-offs between them.
- Co-design noise features with Speed, Power, Reliability, Circuit Design , Power-Arch, ASIC, and platform teams. You're the connective tissue across the codesign web.
- Work with other team members to define product-level voltage noise targets, drive them to closure, and sign them off at shipment.
- Build and take ownership of the Sim-to-Si correlation methodology for noise. You know when a model is lying and when silicon is.
- Model and prototype next-gen noise features - transient sense, droop response, mitigation IP, and codify them so every future program inherits them.
- Lead show-stopper noise bugs during bringup. The critical issues stop with you.
- Drive architecture-level codesign tradeoffs across V/F <-> Power <-> Noise <-> Reliability <-> Thermal (Noise-Variation) and (Noise-to-Closure) boundary work, where the highest-leverage innovation lives.
What we need to see:- BS / MS / PhD in EE, CE, or related (or equivalent experience).
- 5+ years in silicon power integrity, voltage noise, or PDN.
- Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, decap budgeting, voltage regulator response.
- Hands-on silicon experience: bringup, characterization, correlation. You're comfortable on a bench with scopes, probes, DAQ - and in front of a simulator.
- Strong Sim-to-Si correlation instincts - the field of figuring out which side of the equals sign is wrong.
- System-level objectivity. You're willing to make the call that's right for the product even when no single component team agrees with you.
- Multi-functional collaboration in a matrixed environment. You can drive a decision through five collaborators without burning bridges, and you write it down when you're done.
- Spec rigor. We live in spec lock, sign-off, and OPP closure - the work isn't done until it's documented and shipped.
Ways to stand out from the crowd:- Patents or publications in power integrity, voltage noise, PDN, or di/dt mitigation.
- Hands-on with groundbreaking GPU, CPU, or AI accelerator silicon - Hopper / Blackwell / Rubin-class or hyperscaler equivalents.
- ML/AI applied to noise modeling, transient prediction, droop response, or feature optimization. We're rebuilding our toolchain around AI, and noise is squarely in scope.
- Multi-rail, multi-domain PDN ownership at SoC level - die + package + board co-optimization in production.
- Track record of codifying methodology into reusable workflows or tooling.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until June 28, 2026.
This posting is for an existing vacancy.
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