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X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
Mountain View, CA, USA; Austin, TX, USA.
Minimum qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience with high-speed digital design, implementation, and Power, Performance, and Area (PPA) optimization.
- Experience with sign-off convergence domains, including Static Timing Analysis (STA), electrical checks, or physical verification.
Preferred qualifications: - Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with advanced process nodes (e.g., 5nm, 3nm, 2nm, or below).
- Experience applying AI/ML-assisted techniques for physical design closure and PPA scaling.
- Proficiency in scripting (Python, Tcl, Perl) and data mining for QoR metrics.
- Understanding of EMIR flows, power grid design, and design reliability for high-frequency circuits.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $163000 - $236000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities - Partner with architecture, RTL, and DFT teams to optimize power, performance, and area trade-offs.
- Own block and IP-level physical design implementations from synthesis through place and route.
- Debug critical timing paths and apply advanced physical design techniques to solve timing challenges.
- Execute signoff activities, including static timing analysis, power recovery, and electrical layout checks.
