About the EngagementThe I/O chiplet connects die-to-die interfaces with multi-protocol high-speed I/O, combining UCIe, PCIe, Ethernet, static switching, and an embedded management subsystem. You will collaborate with architecture, RTL, verification, firmware, physical design, and IP partners. Client identity and detailed program specifications are shared under confidentiality during interviews.
About the PositionYou will translate architectural requirements into synthesizable SystemVerilog and Verilog, owning assigned blocks from specification through front-end sign-off. The role combines custom datapath and control logic with integration of third-party protocol and PHY IP, with close attention to power, performance, area, and physical implementation.
Key Responsibilities- Define block micro-architecture, interface specifications, and measurable latency, throughput, and resource budgets.
- Develop configurable static-switch fabrics, protocol multiplexers, pipelined datapaths, and boundary rate-adaptation logic.
- Configure and integrate protocol and PHY IP, including clocking, reset, status, and control interfaces.
- Implement CSR access, configuration sequencing, interrupts, and management logic alongside the firmware team.
- Write assertions and resolve lint, clock-domain crossing (CDC), reset-domain crossing (RDC), and connectivity findings.
- Develop timing constraints, analyze synthesis results, and work with physical design on partitioning, congestion, and timing closure.
- Implement low-power controls and support power-intent checks, DFT integration, and formal equivalence activities.
- Debug failures with verification engineers, maintain design documentation, and deliver reviewed RTL and synthesis handoffs.
Must-Have Qualifications- Extensive hands-on ASIC RTL design experience, 10 years or more, with ownership through successful tape-out.
- Strong SystemVerilog and Verilog skills and experience translating specifications into clear, maintainable RTL.
- Depth in high-bandwidth datapaths, pipelining, multiplexing, and multi-clock design.
- Practical experience integrating complex IP and working with at least one high-speed interface such as PCIe, Ethernet, or die-to-die interconnect.
- Strong understanding of CDC/RDC, reset sequencing, assertions, and static design checks.
- Hands-on synthesis, timing constraints, and timing-report analysis; ability to resolve issues with physical design.
- Scripting skills in Python, Tcl, or similar languages to automate design flows.
- Ability to own technical decisions, lead design reviews, and communicate risks and progress clearly.
Nice-to-Have- UCIe or other chiplet interconnect experience, including protocol-to-PHY integration and advanced packaging constraints.
- PCIe Gen6/Gen7, 200G Ethernet, or 224G PAM4 SerDes integration experience.
- Advanced-node ASIC delivery, low-power design with UPF, or physically aware RTL partitioning.
- Embedded RISC-V subsystems, AXI/APB, secure boot, sideband management, or FPGA prototyping experience.
Work ArrangementOttawa, Canada, is preferred. Hybrid arrangements may be considered based on the candidate and project needs. Clear written communication, independent execution, and collaboration with distributed engineering teams are essential.
CompensationCompensation will reflect individual experience, technical capability, and the responsibilities of the role. The package will be discussed during the recruitment process.
Only candidates selected for an interview will be contacted.
