Senior FPGA Architect - Compute Test DivisionOpportunity OverviewTeradyne's Compute Test Division develops advanced test solutions for next-generation silicon, including high-performance SoCs and accelerators powering modern compute and AI systems.
We are seeking a
Senior FPGA Architect to play a key role in architecting and delivering high-performance FPGA-based solutions at the heart of our test platforms. This role involves working at the intersection of FPGA design, board-level hardware, and system architecture-solving complex problems involving high-speed interfaces, tight timing margins, and system-level constraints.
You will collaborate with cross-functional teams to design and deliver robust, scalable solutions that directly impact the quality and performance of cutting-edge semiconductor devices.
Key Responsibilities- Drive FPGA design from architecture through implementation and bring-up, including requirements definition and trade-off analysis
- Architect and implement high-performance FPGA solutions involving complex interfaces and subsystem integration
- Partner closely with hardware, software, and system engineering teams to deliver cohesive system-level solutions
- Lead timing closure, resource optimization, and performance tuning for advanced FPGA designs
- Define and execute validation strategies, including lab bring-up, debug, and root cause analysis using JTAG and lab instrumentation
- Contribute to PCB and system design decisions impacting FPGA performance and integration
- Develop automation and debug tools using scripting (TCL, Python) to improve design and validation workflows
Qualifications (Must-Have)- 8+ years of hands-on experience in FPGA design and development
- Deep expertise in Verilog/SystemVerilog for design and debugging
- Proven experience with AMD (Xilinx) and/or Intel FPGA toolchains, including synthesis, implementation, and timing closure
- Strong understanding of digital design fundamentals and ability to interpret schematics
- Experience with high-speed interfaces such as PCIe, DDR, SerDes, or similar
- Demonstrated ability to bring up and debug FPGA designs on hardware platforms
- Experience with protocols such as AXI4, USB, I2C, SPI
- Scripting proficiency (TCL, Python) for automation and tooling
- Experience with version control systems and collaborative development workflows
Nice-to-Have- Experience with SystemVerilog-based verification methodologies (UVM or similar)
- Familiarity with FPGA SoCs and embedded processor subsystems
What Sets You Apart- Strong system-level thinking and ability to debug across FPGA, board, and software boundaries
- Ability to balance architectural decisions with implementation constraints
- Excellent communication and collaboration skills in cross-functional environments
Compensation:The base salary range for this role is $164,800 - $263,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.
Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.
Benefits:Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.
This position is located at our North Reading, MA development center.
This position is not eligible for visa sponsorship.
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