Job Details:

Job Description:

Intel is seeking a Senior EDA Software Engineer for the Silicon Chassis team. In this technical hands-on leadership role, you will help define end-to-end automation strategy and lead development of the chassis automation tool. Chassis refers to non-compute infrastructure in any soc, which provide essential platform services and typically include interconnects, protocol bridges, clock/reset/power, security, debug/trace/analytics (DTA), RAS error logic, address maps, firmware tables etc. The chassis automation tool will collect user requirements, and translate these requirements into chassis parameters, topology and generate RTL, register definitions, integration and verification collateral for the chassis using highly parameterized and configurable sub-components.

You will work directly with chassis architecture, RTL design, verification, and SOC integration teams to encode the architectural rules of the interconnect and develop a reliable, testable automation framework. You will also mentor the junior engineer joining alongside you. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.

Why This Role Is Exciting :

• Build a brand new automation platform by defining the tool, schema, and methodology from the ground up.

• Directly influence next-generation SoC chassis architectures and delivery.

• Collaborate across architecture, RTL, DV, and SoC integration teams.

• Drive technical direction and establish best practices with broad organizational impact.

Key Responsibilities

• Architect, design, and implement a new chassis automation tool to meet requirements across multiple SoC programs, ensuring scalability, maintainability, and extensibility.

• Analyze chassis and interconnect architecture specifications, along with high-level SoC requirements, and build tooling and infrastructure to translate these requirements into generated outputs such as RTL, RDL, verification collateral, timing, and integration artifacts.

• Develop automation flows that convert architectural intent into concrete implementations, including topology generation, parameter derivation, register definitions, and associated collateral.

• Integrate with frontend and backend tool flows to enable robust validation and quality checks across generated artifacts (e.g., RTL, Verilog, SDC, RDL), ensuring correctness and consistency.

• Enable Power, Performance, and Area (PPA) optimization loops by building automation and analysis capabilities that evaluate design trade-offs and guide configuration decisions.

• Work closely with architecture, RTL design, verification, and SoC integration teams to ensure the tool accurately captures requirements and produces outputs that meet downstream expectations.

• Participate in and contribute to technical reviews with cross-functional stakeholders, incorporating feedback to improve tool capabilities, usability, and quality.

• Drive end-to-end execution from initial concepts and specifications through development, deployment, and ongoing maintenance of the automation framework.

• Lead delivery of the tool and associated outputs to multiple internal customers, balancing competing requirements, schedules, and priorities while maintaining high quality.

• Collaborate across organizational boundaries and contribute beyond immediate role scope when needed to unblock execution and ensure overall program success.

• Mentor and guide engineers, helping establish best practices in software design, testing, and maintainability, and elevating overall team effectiveness.

The ideal candidate will possess the following behavioral traits:

• Ability to interpret architecture or micro-architecture specifications and translate them into robust software implementations.

• Excellent communication, problem-solving, and organizational skills, with a track record of delivering high-quality solutions on schedule.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or a related field, with 9+ years of experience in CAD/EDA tooling, design automation, or semiconductor development OR Master's degree in Electrical Engineering, Computer Science, or a related field, with 8+ years of experience in CAD/EDA tooling, design automation, or semiconductor.

• 5+ years' experience of building scalable, maintainable software systems and frameworks rather than one-off scripts.

• 4+ years' experience in Python or similar language designing and validating structured schemas using formats such as JSON or YAML.

• 2+ years' experience with digital SoC design concepts, including RTL hierarchy, synthesis flows, and parameterized IP design.

• 2+ years' experience with System Verilog to understand and validate generated design outputs.

• 2+ years experience templating systems or code generation frameworks used for structured RTL or collateral generation.

• 1+ years experience with version control (Git), code reviews, unit/integration testing, and CI/CD practices.

Preferred Qualifications:

• Experience building and developing EDA tooling

• Experience with Network-on-Chip (NoC) architectures or high-performance interconnect protocols such as AXI, CHI, PCIe, UCIe, or similar.
  Familiarity with IP packaging, configuration, and integration methodologies, including standards such as IP-XACT.

• Exposure to industry EDA tools and design flows.

• Knowledge of graph-based algorithms (e.g. NetworksX ) and data structures relevant to topology generation, connectivity modeling, or routing problems.

• Prior experience working in a semiconductor product development environment, such as CAD, RTL design, or verification.

• Experience in GUI development

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Benefits at Intel

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

Job Type:
Experienced Hire

Shift:
Shift 1 (United States of America)

Primary Location:
US, California, Santa Clara

Additional Locations:

Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Position of Trust
N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $173,660.00-330,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.