Astera Labs

Senior Digital Design Engineer

Astera Labs • $145K — $175K *
Enterprise Technology
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's degree in Electrical Engineering; Master's preferred.
  • Strong professional attitude and ability to juggle multiple tasks effectively.
  • Entrepreneurial, open-minded, and self-motivated.
  • Authorized to work in the US and available for immediate start.
  • Hands-on experience with high-speed protocols such as PCI-Express.

Responsibilities

  • Develop and implement micro-architecture for front-end circuit designs.
  • Conduct RTL design, simulation, and synthesis for high-performance network controllers.
  • Integrate IP components into existing designs efficiently.
  • Ensure compliance with design for test (DFT) standards.
  • Utilize UVM for design verification processes.

Benefits

  • Encouragement of diverse ideas and backgrounds.
  • Inclusive workplace culture supporting various communities.
  • Opportunities for creativity and innovation in teams.
Full Job Description
Job Description

We are looking for Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration for high performance network controllers. The candidate is preferred to have knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.

Basic Qualifications:
  • Strong academic and technical background in electrical engineering. A Bachelor's degree in EE is required, and a Master's degree is preferred.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks.
  • Entrepreneurial, open-mind behavior and can-do attitude.
  • Authorized to work in the US and start immediately.

Required Experience:
  • Hands-on, prefer knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
  • Proven front end design skill - architecture, RTL, simulations and synthesis
  • Experience with Synopsys and/or Cadence digital design tools/flows
  • Knowledge of design for test (DFT)
  • Familiarity with UVM based design verification
  • Silicon bring-up and debug experience

Preferred Experience:
  • Scripting with Python or other equivalent programming languages.
  • Development/support for PCIe or Ethernet Switch products.


We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About Astera Labs

Astera Labs is a semiconductor company that designs and develops purpose-built connectivity solutions for data-centric systems. The company's portfolio of products includes system-aware semiconductor integrated circuits (ICs), boards, and intellectual property (IP) that are used in data center servers, storage, and networking equipment. Astera Labs' products are designed to improve the performance, latency, and power consumption of data-centric systems. The company was founded in 2018 and is headquartered in Santa Clara, California.
Learn more about Astera Labs
Size
51 employees
Industry
Net Income
-$3 million
Founded
2018
Revenue
$5 million
NASDAQ

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