About the Role

We are seeking a visionary, user-focused Senior Application Engineer / Solutions Architect with a deep background in Electrical Engineering and hands-on experience in RF design environments to shape the user experience and application strategy for our advanced semiconductor design platform.

In this role, your primary responsibility is to be the active voice of the engineer. You will regularly meet with users, design teams, and early adopters to deeply understand their workflows, friction points, and domain challenges in 3D Heterogeneous Integration (3DHI), high-frequency RF, mmWave, and emerging photonic architectures. You will bridge these human insights directly into our platform architecture, translating user pain points into technical design guidance, API ergonomic requirements, and feature specifications for our core software engineering teams.

Combining your expertise in RF EDA tools with script-level programming, you will validate programmatic workflows, build realistic reference designs, and collaborate closely with system architects and software leads to shape API ergonomics, layout editing capabilities, and automated verification flows that define the next generation of programmatic EDA software.

Responsibilities

User Discovery & Pain Point Translation: Actively meet and engage with user engineering teams to study their day-to-day design flows, identify critical bottlenecks in 3DHI and RF packaging, and synthesize user feedback into actionable platform design guidance and technical requirements for software R&D.

Product Strategy & User-Centric Design: Serve as the internal domain authority on RF, mmWave, and advanced packaging workflows, ensuring that platform APIs, data models, and automation features reflect the real-world mental models and needs of electrical engineers.

Agentic Flow Prototyping & Scripting: Write Python scripts, API integration tests, and programmatic workflow examples to validate automated layout and schematic operations, ensuring tools remain intuitive and accessible to domain engineers without computer science backgrounds.

Cross-Domain Workflow Expansion: Define evaluation flows and test cases for emerging 3DHI domains based on user-reported priorities.

Reference Designs & Benchmarking: Build and maintain end-to-end reference design flows and benchmarks to stress-test platform capabilities, automated design space exploration, and simulator integrations under realistic engineering conditions.

Bridging Users & R&D: Work closely with internal software architects and developers to advocate for user priorities, guide API ergonomic decisions, and validate that new platform releases directly address customer pain points.

Qualifications

Required Qualifications

• Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
• Direct, hands-on experience running, debugging, and resolving standard physical verification flows-specifically Design Rule Checking (DRC) and Layout Versus Schematic (LVS) error reports
• Familiarity with electronic design and packaging abstractions, such as schematic connectivity, physical layout hierarchies, netlisting, or multi-die 2.5D/3D packaging concepts.
• Practical experience automating layout tasks, verification runs, or design setups using Python libraries or native EDA scripting interfaces (e.g., Python DSLs, PyAEDT, SKILL, or TCL).
• Strong interpersonal and communication skills with a passion for interviewing engineers, gathering workflow requirements, and converting qualitative user feedback into structured technical guidance.

Preferred Qualifications

• Prior experience in an Application Engineering, Technical Marketing, or Solutions Architecture role within the EDA or semiconductor IP industry.
• Strong understanding of high-frequency RF/microwave circuit concepts, 2.5D/3D packaging structures (micro-bumps, TSVs, interposers), electromagnetic coupling, or signal integrity.
• Experience configuring or running multi-technology assembly verification, interposer DRC/LVS, die-to-die connectivity extraction, or 3D-IC verification flows.
• Experience with C++/Rust.
• Conceptual understanding of AI agentic frameworks, automated optimization algorithms, or LLM-driven developer tooling in engineering contexts.

The level of role will be based on applicable experience, education and skills; Most offers will be between the minimum and the midpoint of the Salary Range listed below.

CA pay range: MIN $156,740- MAX $261,230

Note: For other locations, pay ranges will vary by region

This role is eligible for our Keysight Results Bonus Program

US Employees may be eligible for the following benefits:

• Medical, dental and vision
• Health Savings Account
• Health Care and Dependent Care Flexible Spending Accounts
• Life, Accident, Disability insurance
• Business Travel Accident and Business Travel Health
• 401(k) Plan
• Flexible Time Off, Paid Holidays
• Paid Family Leave
• Discounts, Perks
• Tuition Reimbursement
• Adoption Assistance
• ESPP (Employee Stock Purchase Plan)
• Restricted Stock Units

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