Position Summary: The Semiconductor Packaging Research Engineer drives technology research for advanced packaging and heterogeneous integration. The role is suited for candidates with expertise in either packaging process integration or modeling/simulation, with a focus on evaluating new architectures, materials, interconnects, reliability risks, and manufacturability trade-offs for future products.
Key Responsibilities - Research advanced packaging concepts such as chiplets, heterogeneous integration, 2.5D/3DIC, hybrid bonding, interposer, and die-to-die interconnects.
- Drive either process integration learning or modeling/simulation to assess feasibility, reliability, manufacturability, and technology readiness.
- For process integration: define integration flows, research vehicles, DOE, defect/yield learning, qualification evidence, and risk mitigation paths.
- For modeling: develop and validate thermal, thermo-mechanical, electrical, reliability, or multi-physics models using experimental and failure analysis data.
- Translate product needs into research hypotheses, technical plans, and recommendations; document outputs through reports, design guidance, IP, publications, and development-transfer inputs.
- Collaborate across research, design, process, materials, reliability, manufacturing, supplier, university, and ecosystem teams.
For information on Intel's immigration sponsorship guidelines, please seeIntel U.S. Immigration Sponsorship InformationQualifications:Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Required Qualifications - Master's or Ph.D. in Mechanical Engineering, Electrical Engineering, Materials Science, Applied Physics, Computational Mechanics, Microelectronics, Semiconductor Manufacturing, or related field.
- 1+ years' experience in semiconductor packaging research, advanced packaging integration, process integration, modeling/simulation, reliability, materials, or heterogeneous integration.
- 1+ years' experience in one or more of the following areas: process integration, research vehicle execution, DOE, defect/yield learning, reliability, model development& validation, or multi-physics simulation.
- 1+ years' experience with advanced packaging technologies such as flip chip, chiplets, 2.5D/3DIC, fan-out, hybrid bonding, interposers, HBM integration, advanced substrates, or die-to-die interconnects.
Preferred Qualifications - Ph.D. or deep technical specialization in packaging process integration, computational mechanics, thermal sciences, electrical modeling, materials reliability, or microelectronics research and 4+ years of relevant experience.
- Experience with prototype builds, technology readiness assessment, research-to-development transfer, package-system co-optimization, or chip-package-board co-design.
- Modeling tool experience such as ANSYS, Abaqus, COMSOL, HFSS, Cadence, MATLAB, Python, JMP, or equivalent platforms.
- Record of patents, publications, conference presentations, technical reports, methodology development, or competitive technology assessments.
- Ability to turn ambiguous research problems into clear assumptions, experiments, learning milestones, qualification metrics, and actionable recommendations.
Key Competencies - Advanced packaging research and pathfinding
- Process integration or modeling/simulation expertise
- Heterogeneous integration, chiplet, and advanced substrate knowledge
- DOE, prototype learning, reliability assessment, or model validation
- Technology readiness evaluation and cross-functional communication
Success Measures- Research outputs identify credible integration options, technology limiters, and trade-offs for future platforms.
- Process integration or modeling results are supported by clear assumptions, evidence, validation data, and documented limitations.
- Prototype, DOE, or simulation learning improves feasibility, reliability, integration robustness, and manufacturability understanding.
- Key risks are identified early with practical mitigation paths and development-transfer recommendations.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
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Job Type:College Grad
Shift:Shift 1 (United States of America)
Primary Location:US, Arizona, Phoenix
Additional Locations:US, Oregon, Hillsboro
Position of TrustN/A
BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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