About the role:We're looking for a seasoned RTL Design Tech Lead to drive micro-architecture, RTL development, and technical execution for complex ASIC/SoC programs. This role combines
deep hands-on design expertise with
technical leadership, guiding teams from architecture through tapeout.
The ideal candidate has strong ownership mindset, has led successful silicon bring-ups, and can operate effectively in both structured and fast-paced environments.
This candidate must be willing to be an individual contributor, while leading others. This is an
on-site role and will require presence in the
office 5 days a week. No hybrid option is available.
What you'll do:- Own end-to-end RTL design for major subsystems or full-chip blocks
- Define micro-architecture aligned with PPA (Power, Performance, Area) targets
- Lead and mentor a team of RTL engineers (junior to senior ICs)
- Drive design reviews, coding standards, and best practices
- Collaborate closely with:
- Design Verification (DV)
- Physical Design (PD)
- STA / Timing / DFT teams
- Ensure high RTL quality via:
- Lint, CDC, RDC checks
- Low-power (UPF) compliance
- Debug complex issues across:
- RTL simulation
- Gate-Level Simulation (GLS)
- Silicon bring-up
- Work with foundry and backend constraints (timing, congestion, IR, etc.)
- Drive schedule, risk mitigation, and execution toward tapeout
Required Qualifications:- Bachelor's or Master's in Electrical / Computer Engineering
- 10+ years of experience in ASIC/SoC RTL design
- Expert-level proficiency in:
- SystemVerilog / Verilog RTL coding
- Micro-architecture design
- Strong understanding of:
- Timing (setup/hold, STA correlation)
- CDC/RDC methodologies
- Reset strategies and clocking architectures
- Low-power design (UPF/CPF)
- Proven experience leading blocks through multiple tapeouts
- Hands-on experience with synthesis (e.g., Design Compiler)
- Strong debugging and problem-solving ability
- Excellent communication across cross-functional teams
- Ownership and accountability for silicon success
- Ability to operate under tight tapeout schedules
Preferred Qualifications:- Experience in advanced nodes (e.g., 12FFC, 7nm, 5nm)
- Strong GLS expertise (SDF, X-propagation, power-aware sims)
- Knowledge of DFT (scan, MBIST, compression)
- Experience with high-speed IPs (DDR, PCIe, SerDes) or memory subsystems
- Scripting proficiency (Python / Tcl)
- Prior collaboration with foundries such as TSMC
- Experience in startup environments or first-silicon efforts
- Exposure to packaging (flip-chip, bump planning, IO constraints)
- Experience with low-frequency testchips or rapid prototyping
- Government clearance is preferred
Leadership Expectations:- As an IC, you will provide technical direction and architectural clarity
- Mentor and grow team members
- Drive high engineering standards and design quality
- Influence cross-functional decisions
- Balance hands-on work with leadership responsibilities
Compensation Range: $220,000-$250,000 per year (California). This range represents the anticipated base pay for this role; the final offer may vary based on qualifications, experience, and location.
Benefits:- Medical, Dental, & Vision - 100% covered premiums
- Equity - Stock Options
- 401(k) match
- WFH Hardware
