Signal Integrity & Power Integrity Engineer

DensityAI

$250K — $350K *
Telecommunications & Hardware
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • 5+ years of experience in signal integrity (SI) and power integrity (PI) analysis on high-performance designs at advanced technology nodes (7nm or better)
  • Proficiency in high-speed interfaces such as PCIe, DDR/LPDDR, HBM, and 112G+ SerDes
  • Hands-on experience with industry-standard SI/PI tools including Ansys HFSS, SIwave, Cadence Sigrity, and Keysight ADS
  • Expertise in SI/PI analysis techniques like link budgeting, channel modeling, and thermal-aware signoff
  • Strong collaboration skills with packaging, PCB, and architecture teams for SI/PI budget signoff

Responsibilities

  • Own the signal-integrity and power-integrity analysis and signoff across silicon, package, board, and system
  • Model and sign off high-speed interface channels and power-delivery networks
  • Develop and utilize AI-assisted tool flows for SI/PI modeling and extraction
  • Set and maintain SI/PI budgets collaboratively with various engineering teams
  • Oversee decoupling strategy and ensure compliance with high-speed design standards

Benefits

  • Equity grant per company guidelines
  • Comprehensive medical, dental, and vision insurance
  • 401(k) retirement savings plan
  • Standard paid time off (PTO)
  • Visa sponsorship available for qualified candidates, including H-1B and STEM-OPT
Full Job Description
About the role

Own the signal-integrity and power-integrity engineering that keeps our AI accelerator running clean - across die, package, and board. You'll model and sign off the high-speed interface channels and power-delivery networks that move data and power through the system, set the SI/PI budgets the design is built to, and partner closely with the package, PCB, physical-design, and architecture teams to meet them. This is a deep-expertise, signoff-owning role at the intersection of high-speed design and power delivery: where the electrical realities of advanced-node, high-bandwidth silicon collide with aggressive performance targets, your analysis is what gives the team the confidence to tape out and build.
What will you do
  • Own signal-integrity and power-integrity analysis and signoff for DensityAI's AI platform across silicon, package, board, and system - high-speed interface channels, power delivery, and decoupling strategy
  • Use and develop AI assisted tool flows to accelerate SI/PI modeling, extraction, and signoff timelines
What we're looking for
  • Exceptional abilities across SI/PI analysis: link budgeting, channel modeling and S-parameter extraction, IBIS-AMI, IR-drop and power-delivery-network (PDN) analysis, and EM/thermal-aware signoff
  • 5+ years of SI/PI experience on very high-performance designs at advanced technology nodes (7nm or better) and high-speed interfaces (PCIe, DDR/LPDDR, HBM, 112G+ SerDes, or equivalent)
  • Hands-on with industry-standard tools (Ansys HFSS / SIwave / RedHawk, Cadence Sigrity / Clarity, Synopsys, Keysight ADS or equivalent) for extraction, EM, and PDN analysis
  • Demonstrated ability to work closely with package, PCB, physical design, and architecture teams to set and sign off SI/PI budgets across die-package-board
  • (Optional) 2.5D / 3D and multi-die packaging (CoWoS, EMIB, chiplets, HBM interfaces), jitter / equalization design, co-packaged optics, or post-silicon SI/PI correlation and lab validation
Compensation

Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship

DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls

Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

Full compensation packages are based on candidate experience and relevant certifications.

California pay range

$250,000-$350,000 USD

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