The OpportunityWe are seeking an energetic and detail-oriented
Product and Test Engineer with approximately 5 years of semiconductor industry experience to join our growing High Voltage Power (HVP) business unit. In this role, you will be responsible for developing, debugging, and sustaining production test solutions for our state-of-the-art isolated gate drivers. You will collaborate closely with Analog Design, Systems Engineering, and global manufacturing teams from early design through final silicon release.
What You Will DoTest Solution Development (ATE & Wafer Sort)
- ATE Programming: Develop, debug, and optimize test programs on mixed-signal Automated Test Equipment (ATE) platforms (e.g., Teradyne ETS-364/ETS-88, LTX-Credence, or similar mixed-signal testers).
- Wafer Probe & Final Test: Create robust test methodologies for both wafer-level sorting (utilizing probe cards and Scribe Line Monitors) and final packaged testing (using DIB/Load boards and high-speed sockets).
- Stressing & Screening: Implement mandatory DFT methodologies such as Short Voltage Elevation (SHOVE) stress testing, Gate Stress, and IDDQ/quiescent current screening to catch early-life oxide or via defects.
Hardware & Interface Design
- DIB/Load Board Design: Design, verify, and document Device Interface Boards (DIB), load boards, and handler interface hardware.
- High Voltage Safety: Ensure test hardware incorporates proper creepage, clearance, and safety protocols required to test high-voltage devices (working voltages up to 1000V+ and CMTI transients).
Silicon Characterization & Validation
- Data Log Analysis: Execute characterization plans over voltage and temperature corners (-40°C to 125°C/150°C).
- Statistical Analysis: Analyze test data utilizing statistical process control (SPC) tools, DPAT (Dynamic Part Average Testing), and SBL (Statistical Bin Limits) to establish stable production test limits.
- Failure Analysis: Debug and resolve silicon-level and hardware-level test failures during pre-production validation phases.
Cross-Functional Collaboration
- Design & DFT Support: Participate in DFT reviews with Analog/Digital Design Leads to define test modes, trim algorithms, and verify register/EEPROM default configurations.
- APQP Lifecycle Integration: Deliver mandatory PTE documentation (e.g., Test Coverage Summaries, Yield & Test Time Summaries) required to pass major APQP phase gates from Kickoff (KO) to Release to Production (RTP).
What You Will Need- Bachelor's degree in Electrical Engineering, Electronic Engineering, or a related discipline (Master's degree is a plus).
- 2-6 years of experience in semiconductor Product and/or Test Engineering, ideally with high-voltage, analog mixed-signal, or power management ICs.
- Proficiency in writing and debugging ATE test code (C/C++ or specialized tester languages).
- Solid understanding of analog circuit fundamentals (operational amplifiers, LDOs, DACs, ADCs, gate driver stages).
- Familiarity with high-voltage test constraints, high CMTI environments, and galvanic isolation parameters.
- Experience with PCB design software (Altium, PCB Cadence or similar) for load board schematic/layout review.
- Knowledge of statistical analysis tools (such as Galaxy or similar) for yield and data log analysis.
- Highly organized, proactive communicator, and a strong problem solver who enjoys working in a collaborative, cross-functional global team environment.
