We are looking to add a
PrincipalVerification Engineer I to our team. If you enjoy working in a startup environment and are passionate about developing leading-edge phased arrays for satellites, spacecraft, and aerospace systems, we would like to hear from you.
JOB DUTIES AND RESPONSIBILITIES- Lead the evaluation and technical implementation of FPGA and digital design simulation, verification and emulation infrastructure.
- Lead the development, maintenance and phased deployment of continuous integration and regression testing infrastructure.
- Develop state-of-the-art UVMf-based top-level and module-level testbenches using block-to-top best practices for reusability, including both control and data plane stimulation using VIP & System Verilog DPI-C integration with existing MATLAB and Python numerical models.
- Lead the development of reusable custom VIP modules.
- Work closely with the engineering and senior leadership teams to train and mentor engineers at all experience levels on UVMf testbench usage and modern approaches to FPGA/digital design. Work with the modeling and scientific staff to implement DPI-C dataplane verification interfaces into existing MATLAB and Python models.
- Regularly communicate and present on the current state of verification in the industry, and at the company.
- Continually evaluate current processes regarding FPGA and digital design with a focus on Xilinx TLM models and QEMU-RP integration.
- Work closely with vendors to define requirements of future simulation model deliverables.
- Maintain up-to-date knowledge of industry best-practices regarding FPGA and digital design methodologies.
- Work closely with the engineering leadership team to evaluate and non-disruptively implement process improvements.
JOB REQUIREMENTS AND MINIMUM QUALIFICATIONS- A Bachelor of Science (BS) or Master of Science (MS) degree in Computer Science, Electrical Engineering, or Computer Engineering or related engineering discipline.
- Minimum of 9 years of industry experience in verification and automation.
- Expert-level knowledge of FPGA digital design verification techniques including VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC and functional analysis, QEMU and VIP.
- Expert-level knowledge of digital design automation infrastructure, including CI, regression testing and HIL testing.
- Advanced-level knowledge of Linux.
- Advanced-level knowledge of vendor-provided FPGA development tools with a focus on Xilinx tools.
- Desire and ability to train and mentor while maintaining a positive and productive attitude.
- A deep sense of ownership of your work, and for the success of the company.
$168,000 - $199,000 a year
CesiumAstro considers several factors when extending an offer, including but not limited to, the role and associated responsibilities, a candidate's work experience, education/training, and key skills. Full-time employment offers include company stock options and a generous benefits package including health, dental, vision, HSA, FSA, life, disability and retirement plans.
