Marvell Technology

Principal PHY SerDes Validation Engineer

Marvell Technology$150K — $225K *
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's or Master’s degree in Computer Science, Electrical Engineering, or related field; PhD preferred for advanced roles.
  • 10+ years of experience with a Bachelor's degree, 3-5 years with a Master's/PhD in related areas.
  • Strong understanding of high-speed SERDES and PCIe/Ethernet protocols.
  • 5+ years of hands-on experience in High Speed IO testing and validation.
  • In-depth knowledge of SERDES using NRZ or PAM4 signaling; familiarity with Ethernet standards like 10GbE, 100GbE, 400GbE is a plus.
  • Proficient with SERDES characterization test equipment (oscilloscope, BERT, network analyzer).
  • Experience in Python and MATLAB for automation and programming tasks.

Responsibilities

  • Lead PCIe or Ethernet PHY validation in a post-silicon environment.
  • Define and execute the PHY validation/test plan for storage devices.
  • Conduct lab-based silicon bring-up and unit testing of hardware and firmware functionality.
  • Perform high-speed signal validation using test equipment to analyze Eye diagrams, Jitter, and BER.
  • Debug PHY protocol issues on high-speed serial interfaces such as PCIe or Ethernet.
  • Troubleshoot tests using diagnostics, software tools, and hardware analyzers.
  • Collaborate with cross-functional teams and vendors to resolve technical issues.

Benefits

  • Comprehensive employee stock purchase plan with a 2-year look back.
  • Family support programs to balance work and home life.
  • Robust mental health resources to focus on emotional well-being.
  • Recognition and service awards to celebrate employee contributions.
  • Support options related to financial well-being, family support, mental health, and overall recognition.
Full Job Description
Your Team, Your Impact

The Marvell post silicon validation group designs and develops test platforms for validating multi-core Arm-based Network processors and custom ASIC's,
used in many communication infrastructure applications such as 5G base stations, NICs, Data Center and Cloud Computing platforms. The electrical
characterization team is a post silicon validation sub-group focused on the debug and characterization of SERDES interfaces for various applications on the
products. Characterization engineers are responsible for developing test platforms used and automated test suites to characterize the analog interfaces over
process voltage and temperature (PVT) extremes to determine silicon viability for volume production.

What You Can Expect
  • Complete responsibility for PCIe or Ethernet PHY validation in a post-silicon environment.
  • Defining, documenting, executing, and reporting the overall PHY validation/test plan for Marvell storage devices.
  • Lab-based silicon bring-up and unit test execution focused on Physical and PCS layer hardware and firmware functionality, while also extending to the protocol layer of the stack.
  • Perform high-speed signal validation and analysis using various test equipment to measure Eye diagram / Jitter / BER.
  • Analyze and debug issues on the PHY protocol of high-speed serial interfaces (PCIe or Ethernet).
  • Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, and logic/protocol analyzers.
  • Lead collaborative technical discussions to drive resolution on technical issues.
  • Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PCIe or Ethernet PHY.
  • Work closely with customers to address design issues and debug failure cases.


Note: We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

What We're Looking For
  • Bachelor's degree in Computer Science, Electrical Engineering, or a related field and 10+ years of related professional experience, OR a Master's degree and/or PhD in Computer Science, Electrical Engineering, or a related field with 3-5 years of experience.
  • Strong understanding of high-speed SERDES, equalization techniques, and PCIe or Ethernet protocols.
  • 5+ years of experience with High Speed IO testing, debugging, and validation.
  • 5+ years of direct experience in SERDES characterization/design.
  • In-depth knowledge of SERDES interfaces using NRZ or PAM4 signaling for PCIe or Ethernet interfaces; knowledge of relevant Ethernet standards (e.g., 10GbE, 100GbE, 400GbE) is a plus.
  • In-depth working knowledge of test equipment used for SERDES characterization (scope, BERT, network analyzer, etc.).
  • Deep understanding of high-speed electrical signaling principles, differential signaling, and mixed-signal designs.
  • Experience in Python for automation framework development, as well as mathematical programming such as MATLAB.
  • Critical thinking, a problem-solving attitude, and ownership of the group's results.
  • Knowledge of SERDES modeling techniques.
  • Excellent verbal and written communication skills.


Expected Base Pay Range (USD)
150,680 - 225,700, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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About Marvell Technology

Marvell Technology is a semiconductor company that designs and develops analog, mixed-signal, and digital signal processing integrated circuits. The company's product portfolio includes processors, connectivity, storage, and security solutions. Marvell's customers operate in various industries, including data center, enterprise, automotive, industrial, and consumer electronics. The company was founded in 1995 and is headquartered in Santa Clara, California.
Learn more about Marvell Technology
Size
6,729 employees
Market Cap
$30.6 billion
Industry
Net Income
-$277.3 million
Founded
2013
5 Year Trend
+14.2%
Revenue
$2.9 billion
NASDAQ

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