Job Posting Title:Principal Mixed Signal Engineer, Texas Institute for Electronics
----Hiring Department:Operational Services and Strategies
----Position Open To:All Applicants
----Weekly Scheduled Hours:40
----FLSA Status:To Be Determined at Offer
----Earliest Start Date:Ongoing
----Position Duration:Expected to Continue
----Location:AUSTIN, TX
----Job Details:PurposeThe purpose of the Principal Mixed Signals Engineer is to develop next-generation digital subsystems and compute fabrics for 2.5D/3D microsystems, enabling scalable, high-bandwidth integration across AI, HPC, and wireless acceleration platforms. This includes defining architecture specifications, collaborating with teams to optimize performance, and engaging with semiconductor industry partners to shape ecosystem directions.
Responsibilities- Design and develop high-speed mixed-signal I/O circuits for UCIe 2.5D and 3.0D die-to-die interfaces in 2.5D/3D microsystems-enabling robust, low-latency chiplet interconnect across AI, HPC, and defense platforms.
- Architect and optimize SerDes, clock/data recovery (CDR), equalization, and transceiver circuits for high-speed die-to-die and chip-to-chip links, including UCIe, PCIe physical layers.
- Collaborate with packaging, EDA, and system modeling teams to co-optimize mixed-signal I/O performance across heterogeneous integration stacks-accounting for signal integrity, power delivery, crosstalk, and thermal effects unique to 3DHI.
- Lead silicon bring-up, bench characterization, and production testing of high-speed I/O and mixed-signal circuits-developing test methodologies, ATE programs, and yield-improvement strategies from prototype through volume production.
- Engage with industry partners and standards bodies (UCIe Consortium) to influence specification development and ensure TIE's physical-layer implementations remain standards-aligned.
- Mentor internal design teams on mixed-signal design methodologies, high-speed measurement techniques, and production test best practices for multi-die systems.
- Translate mixed-signal design innovations into IP roadmaps and reference designs, driving alignment between research, productization, and customer enablement for UCIe-based chiplet ecosystems.
Required Qualifications - M.S. in Electrical Engineering with emphasis on analog/mixed-signal or high-speed circuit design (or equivalent practical experience).
- 12+ years of experience in mixed-signal or high-speed I/O circuit design for SoC/ASIC, with direct involvement in SerDes, UCIe, or comparable die-to-die/chip-to-chip interface IP.
- Deep expertise in high-speed transceiver design-including TX/RX front-ends, CDR, equalization (CTLE, DFE), PLLs/DLLs, and signal integrity analysis for multi-Gbps links.
- Hands-on experience with silicon bring-up, lab characterization (high-speed oscilloscopes, BER testers, network analyzers), and production test development on ATE platforms.
- Proficiency with industry-standard analog/mixed-signal EDA tools (Cadence Virtuoso/Spectre, Synopsys HSPICE, Ansys HFSS/SIwave) and parasitic-aware simulation methodologies.
- Strong cross-disciplinary collaboration-able to interface with digital design, packaging, EDA, and process engineering teams to close mixed-signal performance across the 3DHI stack.
- Proven record of taking high-speed mixed-signal IP from design through silicon validation and into production.
- Location. Austin, Texas is preferred for close collaboration with our engineering teams and partners. Hybrid work arrangements may be possible, with travel up to 30-50% as needed. (Any flexible arrangement would be subject to university policies and approvals. Working outside of the state of Texas is subject to University review and approval in relation to jurisdictional employment and tax related laws, rules, and regulations.
Preferred Qualifications - Ph.D. in Electrical Engineering with emphasis on analog/mixed-signal or high-speed circuit design (or equivalent practical experience).
- Direct design experience with UCIe 2.5D (single-ended, shoreline-optimized) and/or UCIe 3.0D (hybrid-bonding, ultra-short-reach) physical-layer implementations.
- Familiarity with heterogeneous (multi-material and/or multi-function) integration challenges-including crosstalk modeling, power delivery network design, and signal integrity in 2.5D/3D hybrid-bonding and interposer stacks.
- Experience designing SerDes or high-speed I/O IP at 28 Gbps and above (e.g., 56G/112G PAM4), with end-to-end ownership spanning specification, design, tape-out, silicon characterization, and production test.
- Knowledge of interconnect and chiplet standards (UCIe, BoW, CXL, PCIe Gen 5/6, NVLink, UALink) and their physical-layer requirements and compliance testing.
- Track record of publications, patents, or industry leadership in mixed-signal circuit design, high-speed I/O, or SerDes architectures.
Salary Range TIE pays industry-competitive salaries.
Working Conditions - May work around standard office conditions
- Repetitive use of a keyboard at a workstation
- Use of manual dexterity (ex: using a mouse)
Work Shift - Monday - Friday: Standard and Flexible
Required Materials - Resume/CV
- 3 work references with their contact information; at least one reference should be from a supervisor
Importantfor applicants who are NOT current university employees or contingent workers: You will be prompted to submit your resume the first time you apply, then you will be provided an option to upload a new Resume for subsequent applications. Any additional Required Materials (letter of interest, references, etc.) will be uploaded in the Application Questions section; you will be able to multi-select additional files. Before submitting your online job application, ensure that ALL Required Materials have been uploaded. Once your job application has been submitted, you cannot make changes.
Important for Current university employees and contingent workers: As a current university employee or contingent worker, you MUST apply within Workday by searching for Find UT Jobs. If you are a current University employee, log-in to Workday, navigate to your Worker Profile, click the Career link in the left hand navigation menu and then update the sections in your Professional Profile before you apply. This information will be pulled in to your application. The application is one page and you will be prompted to upload your resume. In addition, you must respond to the application questions presented to upload any additional Required Materials (letter of interest, references, etc.) that were noted above.
Employment Eligibility:Regular staff who have been employed in their current position for the last six continuous months are eligible for openings being recruited for through University-Wide or Open Recruiting, to include both promotional opportunities and lateral transfers. Staff who are promotion/transfer eligible may apply for positions without supervisor approval.
Retirement Plan Eligibility:The retirement plan for this position is Teacher Retirement System of Texas (TRS), subject to the position being at least 20 hours per week and at least 135 days in length. This position has the option to elect the Optional Retirement Program (ORP) instead of TRS, subject to the position being 40 hours per week and at least 135 days in length.
Background Checks:A criminal history background check will be required for finalist(s) under consideration for this position.
--------Compliance:Employees may be required to report violations of law under Title IX and the Jeanne Clery Disclosure of Campus Security Policy and Crime Statistics Act (Clery Act). If this position is identified a Campus Security Authority (Clery Act), you will be notified and provided resources for reporting. Responsible employees under Title IX are defined and outlined in HOP-3031.
The Clery Act requires all prospective employees be notified of the availability of the Annual Security and Fire Safety report. You may access the most recent report here or obtain a copy at University Compliance Services, 1616 Guadalupe Street, UTA 2.206, Austin, Texas 78701.
