HBM product family is growing due to high demand from industry leading semiconductor companies. As a HBM Memory Design Engineer in sustaining role you will be working with teams like Design Engineering (DE), Product Engineering (PE), Process Integration, Packaging and Technology Development (TD) on evaluating silicon issues seen on all the current HBM designs. You will interact with the architecture team to understand new or modified specification requests, and you will work with the team on implementing and verifying the design, supporting the design release to silicon and all future needs arising for the design. You will have an opportunity to rotate to a Design Engineer role and work on the next generation HBM products. Responsibilities will include, but are not limited to: • Design digital, analog, and memory core circuits using complementary metal-oxide-semiconductor (CMOS) logic and transistor-level techniques, from concept through production-ready solutions. • Model parasitics and support design validation, reticle experiments, and required revisions for initial and subsequent tape-outs. • Create and guide optimized floorplans for placement, routing, power delivery networks, sense margins, array timing, and die size, including layout leadership. • Simulate and verify designs using industry-standard tools such as FineSim, HSPICE (Simulation Program with Integrated Circuit Emphasis), FastSPICE, and Verilog hardware description language. • Analyze and optimize power delivery networks to meet performance, reliability, and efficiency targets. • Debug and identify root causes for pre-silicon and post-silicon issues in current High Bandwidth Memory (HBM) products, driving effective solutions. • Collaborate with standards, computer-aided design (CAD), modeling, and verification teams, and lead design reviews and status updates to communicate progress and technical decisions. Minimum Qualifications: • Bachelor's or Master's degree in Electrical Engineering or a related field, or equivalent practical experience. • 8+ years of relevant experience with a Bachelor's degree or 6+ years with a Master's degree. • Extensive knowledge of CMOS circuit design and semiconductor device physics. • Hands-on experience with schematic entry and circuit simulation using Verilog, FastSPICE, and HSPICE. • Strong understanding of timing, area, power, and complexity trade-offs in Dynamic Random-Access Memory (DRAM) or mixed-signal design. Preferred Qualifications: • Experience clearly communicating complex technical concepts in written and verbal form. • Experience with scripting or automation using Python, Tool Command Language (TCL), Perl, or similar. • Exposure to register-transfer level (RTL) design flows in DRAM or foundry processes. • Experience with DRAM product bring-up and silicon debug. • Exposure to advanced packaging technologies such as through-silicon vias (TSV), hybrid bonding, interposers, or similar.