Your Team, Your Impact

Marvell Custom Solutions develops cutting-edge solutions for large AI, cloud data center, and telecom customers. The SoCs encompass best-in-class performance, advanced die-to-die and packaging technology, and optimized low-power techniques.
The Principle Digital IC Design Engineer (DE06T5) is a senior individual contributor responsible for the design, integration, and delivery of complex digital logic for advanced SoC products. This role owns major IP blocks or subsystems and acts as a recognized technical authority within the program or department. Engineers at this level operate with minimal supervision and are accountable for design quality, schedule, and silicon readiness.

What You Can Expect

As a Principal Design Engineer, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs.

Essential Duties and Responsibilities

• Own RTL design, implementation, and integration of complex blocks or subsystems
• Define and influence block-level and subsystem-level micro-architecture
• Develop high-quality, synthesizable RTL using Verilog/SystemVerilog
• Ensure design correctness through lint, CDC, RDC, and peer reviews
• Collaborate with verification, validation, Firmware and synthesis/STA, and physical design teams
• Identify and resolve complex functional, timing, power and integration issues
• Contribute to digital design methodologies and best practices
• Mentor and guide junior engineers
• Participate in design reviews and tape-out readiness

What We're Looking For

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 12+ years of experience in digital IC or SoC RTL design
• Deep expertise in RTL using system verilog design and micro-architecture
• Strong understanding of clocking, reset, and power-aware design, SoC architecture, processor cores, memory, peripheral interfaces through hand on prior experience
• Hands-on experience with lint, CDC, and RDC analysis
• Proven ownership and track record of block or subsystem delivery on production silicon with aggressive development schedules.
• Strong debugging and problem-solving skills and multi-tasking
• Experience with ARM AMBA, PCIE, DDR, LPDDR, I2C/SMBus, I3C, USB, UART, QSPI/SPI
• Hands on experience in interpretive language such as Perl/Python.

Preferred Qualifications

• Experience with large-scale SoC integration
• Familiarity with low-power design techniques
• Exposure to synthesis, STA, or physical design flows
• Experience mentoring engineers or leading technical reviews

Expected Base Pay Range (USD)
158,600 - 237,600, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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