Principal Engineer, PHY/MAC Design (P)

InnoPhase IoT

• $216K — $220K *
Telecommunications & Hardware
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • Master's degree in Electrical Engineering or related field
  • 10 years of relevant experience
  • Experience in ASIC development and/or FPGA prototyping
  • Proficient in RTL design using Verilog and SystemVerilog
  • Strong understanding of Digital Signal Processing theory
  • Experience with WiFi or Cellular Physical Layer
  • Familiarity with tools like VCS, Verdi, and Spyglass

Responsibilities

  • Develop end-to-end simulation frameworks for wireless systems
  • Model propagation channels and RF/antenna behavior
  • Create and refine Digital Signal Processing engines
  • Design micro-architecture and System Verilog RTL
  • Analyze design bottlenecks and suggest optimizations
  • Develop design, verification, and analysis tools
  • Collaborate with Verification and Validation teams on test plans

Benefits

  • Up to 15% domestic travel
  • Opportunity to work on cutting-edge wireless technology
  • Collaborative environment with cross-functional teams
  • Potential for professional growth in a leading tech company
  • Engagement in innovative projects that impact the industry
Full Job Description


Position With: Innophase IOT, Inc.

Position Title: Principal Engineer, PHY/MAC Design

Rate of pay: $216,091- $220,000 per year

Location: San Jose, CA

Job duties:
  • Develop end-to-end simulation frameworks for sophisticated wireless systems.
  • Work spanning the full signal chain from propagation channel modeling and RF/antenna behavior to PHY & MAC protocols and signal processing algorithms.
  • Develop and refine Digital Signal Processing engines for wireless communication systems.
  • Develop micro-architecture, and System Verilog RTL to meet size, timing, and power target.
  • Analyze, and identify bottlenecks in design and provide feedback on micro-architecture, and optimizations.
  • Develop, and refine design, verification and analysis tools and flows.
  • Work closely with Verification, and Validation teams on test-plans, coverage-analysis
  • Work closely with Physical Design teams to provide guidance on Floor planning, specification of constraints, and timing closure.

Education and Experience: Masters degree in Electrical Engineering, or a related field, plus ten (10) years of relevant experience. Must also have:
  1. Experience in ASIC development and/or FPGA prototyping
  2. Experience in RTL design using Verilog, SystemVerilog
  3. Understanding of Digital Signal Processing theory, and mapping to design
  4. Experience in WiFi Physical Layer, or other Physical layer such as Cellular
  5. Experience with VCS, Verdi, Spyglass, or equivalent tools
  6. Experience in synthesis, timing closure for FPGA and ASICs
  7. Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.

*Up to 15% domestic travel.

How to apply:

Principal Engineer, PHY/MAC Design position with Innophase IOT, Inc. in San Jose, California. Duties include Work spanning the full signal chain from propagation channel modeling and RF/antenna behavior to PHY & MAC protocols and signal processing algorithms. Salary range $216,091- $220,000 per year. Up to 15% domestic travel. To apply, direct resumes to [email protected], and reference job title.

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