In this multi-disciplinary role, you will lead the end-to-end delivery of derivative SoCs, focusing on the intersection of RTL design, functional verification, and physical implementation. You will not just execute flows; you will build an AI-augmented "Silicon Factory" that uses machine learning to bridge the gap between architectural intent and GDSII. Your goal is to achieve ultra-fast turnaround times by using AI to predict physical outcomes during RTL coding and to automate the verification of design variants. Key Responsibilities 1. AI-Augmented RTL & Architecture - Physical-Aware RTL: Use ML-based predictors to evaluate RTL code for timing and congestion bottlenecks before synthesis, reducing the number of "RTL-to-GDS" iterations. - Derivative Generation: Develop scripts and Generative AI prompts to automate the creation of RTL wrappers, memory maps, and bus interconnects for design variants. - Logic Optimization: Employ AI to identify redundant logic or clock-gating opportunities to hit aggressive power targets in derivative designs. 2. Intelligent Verification - Automated Testbench Scaling: Build AI-driven verification environments that automatically adjust constraints and coverage goals when a design derivative (e.g., changed cache size or port count) is instantiated. - Smart Regression Management: Use ML to prioritize test cases that are most likely to fail based on historical RTL changes, slashing simulation time and compute costs. - Bug Prediction: Deploy pattern-recognition models to identify "bug-prone" modules in the RTL based on complexity metrics and previous tape-out data. 3. Rapid Physical Implementation - Seamless Handoff: Ensure a "zero-friction" path from RTL to Physical Design by using AI to automatically generate floorplan constraints and timing assertions from the design spec. - Closure Acceleration: Drive the physical implementation of derivatives, using AI to "reuse" placement and routing solutions from parent designs to achieve 10x faster convergence. Qualifications - Education: Minimum of a Master's degree in Electrical Engineering, Computer Science, or Computer Engineering. - Experience: 12-15 years of professional experience in the semiconductor industry, with a focus on: - Full-Stack Hardware Mastery: Proficiency in SystemVerilog for RTL design and UVM for functional verification. - Physical Design Foundation: Solid understanding of Synthesis, P&R, and STA (Static Timing Analysis) to ensure RTL is physically realisable. - ML/AI Integration: Expert Python skills to build and deploy models that interface with both simulation tools (VCS, Xcelium) and implementation tools (Innovus, ICC2). - Data-Driven Flow Dev: Experience using Tcl/Python to extract "features" from simulation logs and implementation reports to train predictive models. - Version Control & CI/CD: Mastery of Git and CI/CD pipelines (Jenkins/GitLab) to manage the high-velocity deployment of design derivatives. Videos To Watch https://www.youtube.com/embed/k-zs4tB6nNc