Job Details:Job Description: The Role and Impact
As a Principal Engineer in AMS IP Architecture, you will play a pivotal role in defining and driving next-generation analog and mixed-signal (AMS) IP architectures that shape the future of Intel's product offerings. You will apply your expertise to develop innovative architectures, signal processing algorithms, and calibration techniques to optimize performance, power, and area across a range of applications. By collaborating with cross-functional teams, you will ensure Intel's AMS solutions deliver exceptional results for diverse segments, from high-performance computing to ultra-low power products.
Business group
This position is part of Intel's cutting-edge architecture and engineering organization. The team is focused on creating industry-leading analog and mixed-signal IPs that enable world-class product solutions. By combining technical innovation with cross-functional collaboration, the group plays a critical role in delivering scalable, high-performance designs that support Intel's broad portfolio of market-leading technologies.
Key Responsibilities
SerDes Modeling: Architected end-to-end PCIe SerDes models (NRZ/PAM4) in MATLAB/Simulink, capturing complex TX/RX equalization behavior.
Sign-Off Compliance: Executed 128Gbps+ link simulations to validate protocol specs and mitigate margin risks prior to tapeout.
Algorithm Development: Designed real-time calibration and adaptation DSP algorithms balancing convergence speed, stability, and power.
Silicon Correlation: Validated simulation models against lab silicon measurements, closing gaps through iterative behavioral updates.
Cross-Functional Collaboration: Partnered with analog, digital, and hardware teams on circuit trade-offs, logic design, and lab bringup.
Customer Support: Resolved technical field issues and performed custom link budget analyses for client channel/module configurations.
Architecture Review: Evaluated early-stage protocol updates and design specs to guarantee system-level feasibility.
Qualifications:• M.Sc. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field with focus on high-speed communications, analog circuits, or signal processing
• Deep expertise in one or more of the following: SerDes modeling in MATLAB or Simulink, high-speed analog CMOS design, DSP techniques for SerDes equalization and timing recovery, or communications theory including equalization, coding, and noise filtering
• Experience analyzing and closing link budgets for NRZ or PAM4 signaling at 100Gbps or higher, accounting for transmitter impairments, channel loss, reflection, crosstalk, and receiver noise
• Hands-on work with SerDes transmitter and receiver architectures, equalization techniques such as FFE, DFE, and CTLE, or CDR loop dynamics and jitter tolerance
• Ability to correlate models with silicon measurements, debug discrepancies systematically, and update models to reflect real-world behavior
• Familiarity with C, Verilog-A, or SystemVerilog for co-simulation or algorithm prototyping is a plus
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location:US, California, Santa Clara
Additional Locations:US, Arizona, Phoenix, US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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