Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 12+ years of experience
Extensive experience in ASIC/IC design with a comprehensive understanding of the IC design flow
Proficient in architecting digital designs and writing specifications
Fluent in Verilog RTL coding and ASIC design methodology
Expertise in digital design implementation, logical synthesis, and DFT insertion
Experience with static timing analysis and place and route constraints
Proficient in formal verification and CDC/RDC checking
Responsibilities
Propose, architect, and design RTL in Verilog for mixed-signal integrated circuits
Collaborate with a highly experienced team of engineers
Apply clocking controls, FSM design, and low power techniques
Participate in design, architecture, and verification reviews
Oversee digital backend design, including synthesis and static timing analysis
Create documentation for design, verification, and test teams
Mentor and train junior engineers and New College Grads
Benefits
Competitive benefits package
Opportunities for professional development and training
Collaborative work environment with experienced engineers
Potential for involvement in innovative projects
Support for work-life balance
Full Job Description
Propose, architect, and design RTL in Verilog for use in a mixed-signal integrated circuit
Contribute as part of a highly experienced team of engineers with extensive cross-functional skill set
Apply clocking controls, FSM design, low power techniques, and high-speed design concepts
Participate in design, architecture, and verification reviews
Oversee digital backend design, including synthesis, static timing analysis, and logic equivalence checking
Create documentation targeting design, verification, and test teams
Assist with the proposal, definition, documentation, and implementation of new features
Mentor and train junior engineers and New College Grad engineers
Qualifications
Education: Bachelor or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with minimum 12+ years of experience
12+ years of direct experience in ASIC/IC design with deep knowledge of the entire IC design flow
Experience in architecting digital designs and writing device-level or sub-system specifications.
Fluent in Verilog RTL coding and ASIC design methodology
Expertise in digital design implementation, including logical synthesis and DFT insertion with high coverage
Experience with static timing analysis and creation of place and route constraints
Proficiency in formal verification, linting, and CDC/RDC checking
Knowledge of asynchronous clock crossings and synthesis implications of RTL
Experience implementing and verifying ECOs on RTL, synthesized, and post-route netlists
Competence in developing design constraints for synthesis, STA, and P&R hand-off
Experience with gate-level simulations and understanding the causes and implications of timing violations
Familiarity with ATPG generation and ATE support (a plus)
Experience in DFT or physical design (a plus)
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
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About Renesas Electronics America
Renesas Electronics America is a leading supplier of advanced semiconductor solutions including microcontrollers, SoC solutions and a broad range of analog and power devices, with operations spanning research, development, design and manufacturing for a wide range of applications.
