Astera Labs

Principal Advanced Packaging Engineer

Astera Labs$205K — $260K *
Telecommunications & Hardware
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • B.S., M.S., or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
  • 8+ years of experience in semiconductor or advanced packaging engineering with technical leadership.
  • Deep expertise in advanced packaging processes including 2.5D/3D integration, flip-chip, hybrid bonding, and others.
  • Experience in silicon photonics chip packaging and EIC/PIC integration.
  • Hands-on experience with advanced packaging materials like underfill, molding compounds, and adhesives.
  • Proven track record of equipment and process qualification with OSAT or tool suppliers.
  • Experience with PDK development and packaging design rule authoring.

Responsibilities

  • Lead R&D for advanced packaging of optical chips including various integration methods.
  • Define and optimize wafer-level, panel-level, or die-level packaging process flows.
  • Drive EIC-to-PIC integration and broader optical device integration efforts.
  • Select and qualify packaging materials for advanced packaging.
  • Partner with OSAT, tool vendors, and material suppliers to advance development.
  • Characterize and improve yield, reliability, and process capability for packages.
  • Develop and maintain packaging PDKs and design rules for products.

Benefits

  • Eligibility for discretionary bonuses and incentives.
  • Comprehensive benefits package.
Full Job Description
Principal Advanced Packaging Engineer:

About the Role

Astera Labs is seeking a Principal Advanced Packaging Engineer to lead R&D for next-generation packaging technologies for optical chips. This is a senior individual contributor role focused on setting technical direction and driving packaging technology development for NPO and CPO products.

Responsibilities
  • Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.
  • Define and optimize wafer-level, panel-level, or die-level packaging process flows.
  • Drive EIC-to-PIC integration and broader optical device integration efforts.
  • Select and qualify packaging materials for advanced packaging.
  • Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development.
  • Characterize and continuously improve yield, reliability, and process capability for NPO and CPO packages.
  • Develop and maintain packaging PDKs and design rules for NPO and CPO products.

Basic Qualifications:
  • B.S., M.S., or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
  • 8+ years of experience in semiconductor or advanced packaging engineering, with demonstrated technical leadership.
  • Deep expertise in advanced packaging processes, including 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, and overmold across wafer-, panel-, and die-level flows.
  • Experience with silicon photonics chip packaging and EIC/PIC integration.
  • Hands-on experience with advanced packaging materials, including underfill, molding compounds, dielectrics, adhesives, or optical-grade encapsulants.
  • Proven track record of equipment and process qualification with OSAT or tool suppliers.
  • Experience with PDK development and packaging design rule authoring.
  • Strong foundation in yield analysis, reliability characterization, and process capability methodologies such as Cpk and SPC.

Preferred Qualifications:
  • Hands-on experience with CPO or NPO product development.
  • Experience with optical coupling or waveguide alignment for photonic integration.
  • Familiarity with DFM and DFT for advanced packaging.

Salary range is $205,000 to $260,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

About Astera Labs

Astera Labs is a semiconductor company that designs and develops purpose-built connectivity solutions for data-centric systems. The company's portfolio of products includes system-aware semiconductor integrated circuits (ICs), boards, and intellectual property (IP) that are used in data center servers, storage, and networking equipment. Astera Labs' products are designed to improve the performance, latency, and power consumption of data-centric systems. The company was founded in 2018 and is headquartered in Santa Clara, California.
Learn more about Astera Labs
Size
51 employees
Industry
Net Income
-$3 million
Founded
2018
Revenue
$5 million
NASDAQ

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