Job Details:
Job Description:
The Role and Impact:
Join Intel as a Mixed Signal Design Verification Engineer, where you will play a pivotal role in ensuring the reliability and functionality of cutting-edge mixed signal components that power Intel's advanced technologies. Your expertise will directly contribute to delivering robust designs that meet critical performance, power, and timing goals. As part of a dynamic team, you'll have opportunities to collaborate across diverse architectural and design groups, drive innovation in verification methodologies, and make a tangible impact on Intel's success in the competitive semiconductor landscape.
Key Responsibilities:
- Develop and execute verification plans for mixed signal components, ensuring comprehensive coverage against architectural and microarchitectural specifications.
- Build and maintain test benches and verification environments to validate functionality, timing, and power requirements.
- Create analog behavioral models and system simulation models to identify and resolve bugs during the presilicon phase.
- Replicate, root cause, and debug issues, implementing corrective measures to resolve failures efficiently.
- Collaborate closely with digital and analog architects, RTL developers, and physical design teams to optimize verification flow and achieve design goals.
- Perform technical reviews of test plans and proofs with design and architecture teams to ensure accuracy and completeness.
- Enhance the functional verification infrastructure and methodologies to improve efficiency and reliability.
- Utilize scripting and advanced tools, including AI-based solutions, to streamline verification flow from test plan generation to test triage.
Qualifications:
Minimum Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 1+ years of experience in design verification roles, or Master's degree with 0+ years of experience.
- Proficiency in SystemVerilog and Verilog for verification purposes.
- Demonstrated experience in debugging presilicon issues and implementing corrective actions.
- Strong problem-solving skills with the ability to analyze complex design challenges.
- Knowledge of scripting languages such as Python for automating verification processes.
Preferred Qualifications:
- Expertise in OVM and UVM methodologies.
- Experience in test environment development and planning to ensure coverage and reliability.
- Familiarity with objection-oriented programming (OOP) principles in the context of design verification.
- Experience leveraging AI-based tools to enhance verification methodologies.
- Ability to collaborate effectively with cross-functional teams and communicate design insights clearly.
- A proactive mindset, aiming to continuously improve verification infrastructure and methodologies.
The Fully Remote Work Model is temporary, once the office is established - The Hybrid Work Model will apply.
Job Type:
Experienced Hire
Shift:
Shift 1 (Canada)
Primary Location:
Virtual Canada
Additional Locations:
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Annual Salary Range for jobs which could be performed in Canada
CAD 109,380.00-154,420.00
Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.
