THE ROLE:

AMD's Datacenter Performance Group is seeking an Engineer for Power Management Architecture and Power and Performance Modeling to support the Power Constrained Performance of our industry-leading AI/ML/HPC GPUs. The role will involve contributing to the Perf@Power attainment of a leading generation of our Instinct accelerators, working closely with a cross-functional team that drives key aspects of Perf@Power attainment, including pre-Si modeling, post-Si correlation, workload analysis, PPA target setting and attainment tracking, power/perf roll-ups and reporting, and methodology development. Being passionate about performance and power efficiency, strong analytical skills, and effective communication are key ingredients for success in this role.

KEY RESPONSIBILITIES:

• Support power-constrained performance modeling, projections, target setting, and attainment tracking from Concept-exit (pre-Si) to Product launch (post-Si) for AMD Instinct AI/ML/HPC accelerators
• Contribute to power management architecture definition across multiple levels, including:
  • Firmware-based power management features (e.g., SMU-driven power/thermal control, power state management)
  • AVFS (Adaptive Voltage and Frequency Scaling) technologies, including RTAVFS, to reduce voltage/frequency margin based on real-time feedback
  • Micro-architecture level power features (e.g., clock gating, power gating, dynamic voltage/frequency scaling, p-states)
  • Macro-architecture level power features (e.g., power domains, power delivery partitioning, on-die voltage regulation)
  • SoC-level power management and power capping features
  • Rack-level and Datacenter-level power management and orchestration features
• Develop and maintain power and performance models to support Cdyn/Leakage/STA/Area trade-off analysis and attainment
• Create state-of-the-art ML-based modeling solutions to improve accuracy, speed, and scalability of power and performance predictions across pre-Si and post-Si stages
• Explore and apply advanced ML techniques (e.g., regression, gradient boosting, neural networks) to model power/performance behavior, automate correlation between pre-Si projections and post-Si silicon data, and accelerate workload power analysis
• Collaborate with product architecture and business unit teams to help define product configurations, capabilities, and P&P targets
• Work cross-functionally with SOC architecture, System Design, IP Design, Circuit Design, Foundry team, CAD, Physical Design, Software, Firmware, Power Management, and Post-Si validation teams to support P&P attainment
• Assist with power/performance roll-ups and readouts, and help drive awareness of power efficiency improvements across teams
• Support post-Si power/performance debug and calibration of pre-Si models against silicon data
• Contribute to workload power analysis and help evolve methodologies for key PPA domains

KEY QUALIFICATIONS:

• Background in Computer Architecture, Processor/Accelerator development, or Power Management Architecture
• Experience or strong interest in firmware-based power management, AVFS technologies, and power features spanning micro-architecture, macro-architecture, SoC, Rack, and Datacenter levels
• Experience or strong interest in power/performance projections, modeling, and optimization at the SoC or system level
• Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc.)
• Familiarity with post-silicon power/performance debug and model correlation is a plus
• Good communication skills and ability to collaborate effectively with various engineering teams
• Familiarity with fundamentals of Machine Learning and hands-on experience with model building is a bonus, with interest in developing new, state-of-the-art ML-based modeling solutions for power and performance prediction
• Knowledge of DL/ML/LLM/MoE workloads will be a bonus

EDUCATION:

• Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related field

This role is not eligible for visa sponsorship.

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Benefits offered are described:  AMD benefits at a glance.