Our Tensix Team is building the next generation of high-performance AI compute systems. We're looking for a Power Architect to drive architectural strategy, modeling, and design decisions that shape how power is understood and optimized across our products. This is a hands-on role with massive influence over how we build power-aware systems from the ground up.
This role is hybrid, based out of Santa Clara, CA.
We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are- 15+ years experience with power estimation tools like PowerArtist, PtPX, RTL Architect, and PrimePower.
- Skilled in modeling and optimizing power at the architectural level, with deep knowledge of power-gating, voltage domains, and leakage control.
- Track record of influencing architectural and micro-architectural changes that meaningfully reduced design power.
- Proficient in Verilog HDL, Design Compiler, C/C++ and Python.
- Background in power-optimization of compute datapath and/or interconnects.
What We Need- Predict power consumption early in architecture and track it through RTL evolution.
- Propose architectural changes for power optimization across server and non-server markets.
- Build workloads that stress real-world use cases and guide thermal and power-delivery solutions.
- Correlate pre-silicon estimates to silicon measurements and drive power efficiency improvements.
What You Will Learn- How AI workloads impact power at every layer of the stack - from circuit to software.
- Challenges in building accurate, CI-integrated power modeling infrastructure.
- Techniques for aligning design tradeoffs to the realities of AI model execution.
- How Tenstorrent approaches full-stack power optimization across chiplet-based systems.
Tenstorrent offers a highly competitive compensation package and benefits.
