Minimum qualifications:- Bachelor's degree in Electronics Engineering, Electrical Engineering, Computer Science, Computer Engineering, or a related field and 3 years of experience in the job offered or in a Silicon Engineer-related occupation.
- Alternatively will accept a Master's degree in Electronics Engineering, Electrical Engineering, Computer Science, Computer Engineering, or a related field and 1 year of experience in the job offered or in a Silicon Engineer-related occupation.
- Position requires 1 year of experience in the following: Microarchitectural development of IP development, or SoC development; and RTL development.
About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The US base salary range for this full-time position is $176,700 - $198,000 15% bonus target equity benefits determined by role, level, and location. Individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training. Learn more about benefits at Google
Position reports to the Google Mountain View, CA office & may allow for a hybrid schedule as per Google policy.
The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.
Responsibilities- Develop, analyze, optimize system-on-chip (SOC) and develop custom IP for silicon designed for Google's consumer devices or other products.
- Develop cutting-edge SOC and IP microarchitecture to ensure best PPA (Power, Performance, Area) in the design.
- Work closely with architect and SW teams to define new IP and its corresponding micro-architecture that provides added value to users.
- Engage in quality checks of front-end design, including writing RTL and running quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, UPF, and Low Power Optimization/Estimation).
- Contribute to development of methodology and tools, to improve the efficiency of designs to meet product requirements.
