Minimum qualifications:- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience in post-layout physical netlist validation or low-power signoff in an ASIC design environment.
- Experience in static low-power rule checking tools (e.g., VCLP or CLP) or debugging signal corruption or structural checks.
- Experience debugging technical issues within the IEEE 1801 UPF framework or the physical gate-level netlist flow.
Preferred qualifications:- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience interacting with Place and Route (P&R) tools (Innovus, Fusion) and an understanding of standard cell timing, hierarchical construction, and physical logic optimization.
- Familiarity with the behavioral nuances of timing-driven P&R algorithms, specifically regarding the insertion, scaling, level shifters and always-on (AON) cells in modern process nodes.
- Effective skills with scripting languages such as Tcl or Python to automate Engineering Change Orders (ECOs) and improve verification workflows.
About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will lead technical engagements to guarantee the electrical and structural integrity of multi-voltage ASICs. You will be the primary point of contact for low power signoff workstreams, managing the validation of physical net lists and ensuring power intent benchmarks are met. You will bridge the gap between front-end voltage domain architecture and physical execution, overseeing the mitigation of post-layout low power anomalies to ensure tape out readiness.
US: $163000 - $237000 (USD) 15% bonus target equity benefits
Responsibilities- Design, deploy, and carry out post-layout low power verification methodologies according to execution schedules and tape-out signoff criteria to ensure successful multi-voltage implementation.
- Validate the implementation of complex multi-voltage design collateral, performing gate-level checks using industry-standard tools (e.g., Synopsys VCLP) to ensure power/ground integrity and UPF alignment.
- Drive the resolution of complex Physical Design and Place and Route (P&R) anomalies, specifically mitigating issues such as wrong domain buffering, secondary power routing failures, and isolation clamping errors.
- Perform targeted debugging on advanced Clock Tree Synthesis (CTS) implementations, analyzing tool behavior around level shifters in high fanout networks, duty cycle distortions, and multi-voltage skew management.
- Drive the continuous refinement of power state tables (PST) and Unified Power Format (UPF) scripts to ensure accurate translation from Golden RTL to the final physical netlist.
