Physical Design Timing Engineer

DensityAI

$220K — $350K *
Telecommunications & Hardware
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • 10+ years of experience in high performance designs at advanced technology nodes (7nm or better)
  • Exceptional abilities across the full physical design flow (synthesis, place & route, CTS, signoff)
  • Hands-on experience with industry-standard PD tools (Cadence Innovus, Synopsys Fusion Compiler, or equivalent)
  • Proven ability to collaborate with architects, RTL designers, EDA vendors, and foundries
  • Post silicon characterization and process targeting experience is highly desirable
  • Optional experience with multi-die packaging or DFT-aware physical design

Responsibilities

  • Own full chip and block timing methodologies and execution to signoff of AI accelerator silicon
  • Utilize and develop AI-assisted tool flows for enhanced physical design timing convergence
  • Drive timing methodologies throughout the design and signoff process
  • Collaborate with chip-design and software teams to support the AI accelerator program
  • Manage timelines for timing flows and ensure alignment across teams

Benefits

  • Equity grant according to company guidelines
  • Medical, dental, and vision insurance
  • 401(k) retirement plan
  • Standard paid time off (PTO)
  • Immigration support for visa sponsorship
Full Job Description
ITAR Notice: This role involves access to ITAR-controlled information. Applicants must be U.S. persons (U.S. citizens, U.S. permanent residents, asylees, or refugees) per 22 CFR 120.62.
About the role

Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out.
What you'll do
  • Own Full chip and Block timing methodologies and execution to-signoff of our AI accelerator silicon.
  • Use and develop AI-assisted tool flows to accelerate physical design timing convergence and signoff timelines.
What we're looking for
  • Exceptional abilities across the full physical design flow (synthesis, place & route, CTS, signoff) with emphasis on timing flows and methodologies
  • 10+ years of experience on very high performance designs at advanced technology nodes (7nm or better) and 2.5D/3D timing flows
  • Hands-on with industry-standard PD tools (Cadence Innovus, Synopsys Fusion Compiler, or equivalent) and signoff (PrimeTime, Tempus, or equivalent)
  • Demonstrated ability to work closely with architects, RTL designers, EDA vendors, and foundries to design and sign off complex chips
  • Post silicon characterization and process targeting experience is highly desirable
  • (Optional) Multi-die packaging (CoWoS, 2.5D / 3D), thermal / IR / EM signoff, signal integrity, or DFT-aware physical design
Compensation

Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship

DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls

Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

Full compensation packages are based on candidate experience and relevant certifications.

California pay range

$220,000-$350,000 USD

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