ITAR Notice: This role involves access to ITAR-controlled information. Applicants must be U.S. persons (U.S. citizens, U.S. permanent residents, asylees, or refugees) per 22 CFR 120.62.
About the roleOwn floorplan-to-signoff physical design for one or more blocks of our AI accelerator silicon. Work with chip-design and software teams driving DensityAI's AI accelerator program from first silicon through scale-out.
What you'll do- Own floorplan-to-signoff physical design for one or more blocks of our AI accelerator silicon
- Use and develop AI-assisted tool flows to accelerate physical design and signoff timelines
What we're looking for- Exceptional abilities across the full physical design flow (synthesis, place & route, CTS, signoff)
- 8+ years of experience on very high performance designs at advanced technology nodes (7nm or better)
- Hands-on with industry-standard PD tools (Cadence Innovus, Synopsys Fusion Compiler, or equivalent) and signoff (PrimeTime, Tempus, or equivalent)
- Demonstrated ability to work closely with architects, RTL designers, EDA vendors, and foundries to design and sign off complex chips
- (Optional) Multi-die packaging (CoWoS, 2.5D / 3D), thermal / IR / EM signoff, signal integrity, or DFT-aware physical design
CompensationFinal offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa SponsorshipDensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export ControlsAspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Full compensation packages are based on candidate experience and relevant certifications.
California pay range
$230,000-$400,000 USD
